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YOSHIHIDE KOMATSU
Author Info
Open Visualization
Name
Affiliation
Papers
YOSHIHIDE KOMATSU
Semicond Technol Acad Res Ctr, STARC, Yokohama, Kanagawa 2220033, Japan
9
Collaborators
Citations
PageRank
41
26
5.22
Referers
Referees
References
75
48
7
Publications (9 rows)
Collaborators (41 rows)
Referers (75 rows)
Referees (48 rows)
Title
Citations
PageRank
Year
A 0.6-V Adaptive Voltage Swing Serial Link Transmitter Using Near Threshold Body Bias Control And Jitter Estimation
0
0.34
2020
A 0.25-27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis.
3
0.51
2019
A 0.25-27Gb/s Wideband PAM4/NRZ Transceiver with Adaptive Power CDR for 8K System
0
0.34
2018
An ultra-wide range Bi-directional transceiver with adaptive power control using background replica VCO gain calibration
2
1.00
2011
Transceiver Macro With Spread-Spectrum Clocking Capability For Ac-Coupled Cable Interfaces
0
0.34
2008
Low-Voltage And Low-Power Logic, Memory, And Analog Circuit Techniques For Socs Using 90 Nm Technology And Beyond
4
0.49
2006
Soft Error Hardened Latch Scheme With Forward Body Bias In A 90-Nm Technology And Beyond
0
0.34
2006
Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias
8
0.82
2005
A soft-error hardened latch scheme for SoC in a 90 nm technology and beyond
9
1.04
2004
1