Paper Info
Title
Instruction set extension with shadow registers for configurable processors
Abstract
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made in the tools and methodologies of automatic instruction set extension for configurable processors, the limited data bandwidth available in the core processor (e.g., the number of simultaneous accesses to the register file) becomes a potential performance bottleneck. In this paper we first present a quantitative analysis of the data bandwidth limitation in configurable processors, and then propose a novel low-cost architectural extension and associated compilation techniques to address the problem. The application of our approach results in a promising performance improvement.
Year
DOI
Venue
2005
10.1145/1046192.1046206
FPGA
Keywords
Field
DocType
promising performance improvement,approach result,novel low-cost architectural extension,shadow register,limited data,core processor,associated compilation technique,automatic instruction set extension,data bandwidth limitation,potential performance bottleneck,configurable processor,system on a chip,embedded system,quantitative analysis,register file
Bottleneck,Bandwidth limitation,Computer science,Instruction set,Real-time computing,Multi-core processor,Shadow,Computer architecture,Parallel computing,Register file,Bandwidth (signal processing),Performance improvement,Embedded system
Conference
ISBN
Citations 
PageRank 
1-59593-029-9
27
1.19
References 
Authors
16
6
Name
Order
Citations
PageRank
Jason Cong17069515.06
Yiping Fan245625.67
Guoling Han331317.17
Ashok Jagannathan41148.54
Glenn Reinman5147694.66
Zhiru Zhang6102071.74