Name
Title | ||
|---|---|---|
Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems |
Abstract | ||
|---|---|---|
This paper considers the problem of increasing the storage density in fault-tolerant VLSI systems which require only limited data retention times. To this end, the concept of storing many bits per memory cell is applied to area-efficient and fully logic-compatible gain-cell-based dynamic memories. A memory macro in 90-nm CMOS technology including multilevel write and read circuits is proposed and analyzed with respect to its read failure probability due to within-die process variations by means of Monte Carlo simulations. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/1973009.1973078 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
logic-compatible multilevel gain-cell-based dram,monte carlo simulation,90-nm cmos technology,read failure probability,storage density,fault-tolerant vlsi system,process variation,failure analysis,memory macro,memory cell,logic-compatible gain-cell-based dynamic memory,limited data retention time,fault tolerant,retention time | Dram,Monte Carlo method,Data retention,Computer science,CMOS,Electronic engineering,Real-time computing,Fault tolerance,Electronic circuit,Macro,Memory cell | Conference |
Citations | PageRank | References |
1 | 0.37 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pascal Andreas Meinerzhagen | 1 | 42 | 5.25 |
| Onur Andiç | 2 | 1 | 0.37 |
| Jürg Treichler | 3 | 1 | 0.37 |
| A. Burg | 4 | 1426 | 126.54 |