Name
Abstract | ||
|---|---|---|
We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophisticated RBF model, the run times of the simulator were within an order of magnitude of the run times for pattern-parallel complete-circuit stuck-at fault simulation. Industrial-size circuits, including a multi-million-gates design, could be simulated in reasonable time despite a significantly higher number of faults to be simulated compared with stuck-at fault simulation. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1403375.1403527 | design, automation, and test in europe |
Keywords | Field | DocType |
benchmark testing,bridge circuits,fault simulation,logic design,logic gates,logic testing,industrial circuits,multimillion-gate design,pattern-parallel complete-circuit stuck-at fault simulation,resistive bridging fault simulation,Resistive bridging faults,bridging fault simulation,case study | Logic synthesis,Stuck-at fault,Logic gate,Bridging fault,Computer science,Resistive touchscreen,Slowdown,Real-time computing,Electronic engineering,Electronic circuit,Benchmark (computing) | Conference |
ISSN | Citations | PageRank |
1530-1591 | 3 | 0.43 |
References | Authors | |
35 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Piet Engelke | 1 | 296 | 16.11 |
| Ilia Polian | 2 | 889 | 78.66 |
| Juergen Schloeffel | 3 | 47 | 5.51 |
| Bernd Becker | 4 | 855 | 73.74 |