Juergen Schloeffel - Citegraph

Author Info

Name	Affiliation	Papers
JUERGEN SCHLOEFFEL	NXP Semicond GmbH, Design Technol Ctr, D-21147 Hamburg, Germany	12
Collaborators	Citations	PageRank
52	47	5.51
Referers	Referees	References
163	396	177

Search Limit

100396

Publications (12 rows)

Collaborators (52 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.	2	0.47	2017
3D DFT Challenges and Solutions	2	0.38	2015
Cell-aware Production test results from a 32-nm notebook processor	2	0.41	2012
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics	9	0.59	2010
Resistive bridging fault simulation of industrial circuits	3	0.43	2008
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults	4	0.42	2007
Computation and Application of Absolute Dominators in Industrial Designs	0	0.34	2007
Fault detection and diagnosis with parity trees for space compaction of test responses	8	0.56	2006
Deterministic logic BIST for transition fault testing	7	0.53	2006
A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips	3	0.55	2005
ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips	2	0.40	2005
Modeling and analysis of crosstalk coupling effect on the victim interconnect using the ABCD network model	5	0.43	2004

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