Name
Title | ||
|---|---|---|
A soft error robust 32kb SRAM macro featuring access transistor-less 8T cell in 65-nm. |
Abstract | ||
|---|---|---|
An eight transistor static random access memory cell with an access transistor-less architecture is presented that shows high soft error robustness and low leakage current. A 32kb memory array is designed in 65 nm CMOS process. The cell provides 5.6x better immunity to soft errors when compared to a conventional SRAM cell. The cell shows 9.4x smaller read current than a 6T SRAM cell. The featured cell also shows read and write margin improvements. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/VLSI-SoC.2012.6379045 | VLSI-SOC |
Keywords | Field | DocType |
CMOS memory circuits,SRAM chips,leakage currents,memory architecture,6T SRAM cell,CMOS process,access transistorless 8T cell architecture,low leakage current,memory array,read-write margin,size 65 nm,soft error robust SRAM macro,storage capacity 32 Kbit,transistor static random access memory cell | Sense amplifier,Soft error,Computer science,Robustness (computer science),Electronic engineering,Static random-access memory,Macro,MOSFET,Transistor,Memory architecture | Conference |
ISSN | Citations | PageRank |
2324-8432 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaspal Singh Shah | 1 | 21 | 2.12 |
| David Nairn | 2 | 8 | 1.36 |
| Manoj Sachdev | 3 | 669 | 88.45 |