Name
Abstract | ||
|---|---|---|
Domain Wall Memory (DWM) is a recently developed spin-based memory technology in which several bits of data are densely packed into the domains of a ferromagnetic wire. DWM has shown great promise in enabling non-volatile memory with unprecedented density and high energy efficiency. In this work, we propose TapeCache, a first attempt to employ DWMs as last-level caches in general purpose computing platforms. DWMs enable much higher density compared to SRAM, DRAM, and other spin-based memory technologies such as STT-MRAM. However, they also pose unique challenges such as serial access to the bits stored in a DWM cell, leading to variable access latencies. We propose a novel circuit-architecture co-design for TapeCache, consisting of (i) a multi-port DWM macro-cell optimized for read operations considering the asymmetry in applications' read/write characteristics, and (ii) a new cache organization and suitable management policies that mitigate the performance penalty arising from serial access to bits in a macro-cell. Over a wide range of SPEC 2006 benchmarks, TapeCache achieves 7.8X improvement in area, an average energy improvement of 7.3X, and an average performance improvement of 1.2% compared to an iso-capacity SRAM cache. Compared to an iso-capacity STT-MRAM cache, TapeCache obtains 2.3X improvement in area and 1.4X average energy savings with virtually identical performance. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2333660.2333707 | ISLPED |
Keywords | Field | DocType |
spin-based memory technology,average energy improvement,multi-port dwm macro-cell,average performance improvement,high density,serial access,dwm cell,tapecache obtains,high energy efficiency,identical performance,domain wall memory,average energy saving,energy efficient cache,cache,domain wall,energy efficient,non volatile memory | Uniform memory access,Cache pollution,CPU cache,Computer science,Cache,Parallel computing,Cache-only memory architecture,Cache algorithms,Real-time computing,Cache coloring,Non-uniform memory access,Computer hardware | Conference |
Citations | PageRank | References |
43 | 2.80 | 10 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rangharajan Venkatesan | 1 | 350 | 19.87 |
| Vivek Kozhikkottu | 2 | 173 | 9.39 |
| Charles Augustine | 3 | 55 | 5.90 |
| Arijit Raychowdhury | 4 | 514 | 71.77 |
| Kaushik Roy | 5 | 7093 | 822.19 |
| Anand Raghunathan | 6 | 5375 | 415.27 |