Name
Abstract | ||
|---|---|---|
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not just a relative ordering between events, but also some forms of metric timing constraints. Circuits modeled using generalized relative timing constraints are formally encoded as timed automata. Novel fully symbolic verification algorithms for timed automata are then used to either verify a temporal logic property or to check conformance against an untimed specification. The combination of our new modeling technique with fully symbolic verification methods enables us to verify larger circuits than has been possible with other approaches. We present case studies to demonstrate our approach, including a self-timed circuit used in the integer unit of the Intel R |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ASYNC.2005.24 | ASYNC |
Keywords | DocType | ISSN |
circuits,conformance testing,formal verification,automata,logic,logic design,design methodology,computer science,decoding,logic simulation | Conference | 1522-8681 |
ISBN | Citations | PageRank |
0-7695-2305-6 | 6 | 0.53 |
References | Authors | |
18 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sanjit A. Seshia | 1 | 2226 | 168.09 |
| Randal E. Bryant | 2 | 9204 | 1194.64 |
| Kenneth S. Stevens | 3 | 185 | 25.65 |