Paper Info
Title
Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing
Abstract
In this paper, the architecture of a novel reconfigurable array, optimized for high-throughput and low-power Digital Signal Processing, is described. The proposed reconfigurable system consists of 2D array of homogeneous coarse-grain reconfigurable cells organized into a hierarchical two-level architecture. The system has been characterized for performing different DSP tasks. Comparison results demonstrate speedups up to 8X with energy efficiency improvement up to 58% over a state of the art FPGA.
Year
DOI
Venue
2008
10.1007/978-3-540-95948-9_30
PATMOS
Keywords
DocType
Volume
energy efficient coarse-grain reconfigurable,low-power digital signal processing,novel reconfigurable array,homogeneous coarse-grain reconfigurable cell,energy efficiency improvement,art fpga,proposed reconfigurable system,hierarchical two-level architecture,comparison result,different dsp task,accelerating digital signal processing,high throughput,energy efficient,digital signal processing
Conference
5349
ISSN
Citations 
PageRank 
0302-9743
0
0.34
References 
Authors
7
4
Name
Order
Citations
PageRank
Marco Lanuzza120328.64
Stefania Perri226433.11
Pasquale Corsonello327838.06
Martin Margala431855.78