| Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions | 1 | 0.40 | 2021 |
| Efficient Deconvolution Architecture for Heterogeneous Systems-on-Chip. | 2 | 0.41 | 2020 |
| Stereo vision architecture for heterogeneous systems-on-chip | 1 | 0.35 | 2020 |
| Approximate Multipliers With Dynamic Truncation For Energy Reduction Via Graceful Quality Degradation | 0 | 0.34 | 2020 |
| An Efficient Convolution Engine based on the À-trous Spatial Pyramid Pooling | 0 | 0.34 | 2020 |
| A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs | 0 | 0.34 | 2020 |
| Design of a real-time face detection architecture for heterogeneous systems-on-chips. | 0 | 0.34 | 2020 |
| UWB TDoA-based Positioning Using a Single Hotspot with Multiple Anchors | 0 | 0.34 | 2019 |
| Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation | 1 | 0.35 | 2019 |
| Efficient Architecture for Integral Image Computation on Heterogeneous FPGAs | 2 | 0.43 | 2019 |
| An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis. | 1 | 0.35 | 2019 |
| Multimodal background subtraction for high-performance embedded systems | 0 | 0.34 | 2019 |
| Design of Efficient BCD Adders in Quantum-Dot Cellular Automata. | 2 | 0.41 | 2017 |
| An efficient hardware-oriented stereo matching algorithm. | 2 | 0.35 | 2016 |
| Design Of Efficient Qca Multiplexers | 0 | 0.34 | 2016 |
| Exploring well configurations for voltage level converter design in 28 nm UTBB FDSOI technology | 2 | 0.42 | 2015 |
| Power supply noise in accurate delay model for the sub-threshold domain. | 0 | 0.34 | 2015 |
| Low-Leakage SRAM Wordline Drivers for the 28-nm UTBB FDSOI Technology | 5 | 0.50 | 2015 |
| Fast and Wide Range Voltage Conversion in Multisupply Voltage Designs | 11 | 0.68 | 2015 |
| A novel background subtraction method based on color invariants and grayscale levels | 0 | 0.34 | 2014 |
| Over/Undershooting Effects in Accurate Buffer Delay Model for Sub-Threshold Domain | 5 | 0.50 | 2014 |
| Analyzing noise robustness of wide fan-in dynamic logic gates under process variations | 1 | 0.35 | 2014 |
| Gate-level body biasing technique for high-speed sub-threshold CMOS logic gates. | 0 | 0.34 | 2014 |
| Design of high-speed low-power parallel-prefix adder trees in nanometer technologies. | 0 | 0.34 | 2014 |
| Adaptive Census Transform: A novel hardware-oriented stereovision algorithm | 8 | 0.61 | 2013 |
| Energy-efficient single-clock-cycle binary comparator | 7 | 0.63 | 2012 |
| Low-cost FPGA stereo vision system for real time disparity maps calculation | 9 | 0.48 | 2012 |
| Analytical Delay Model Considering Variability Effects in Subthreshold Domain. | 11 | 0.72 | 2012 |
| Comparative analysis of yield optimized pulsed flip-flops. | 9 | 0.75 | 2012 |
| Efficient memory architecture for image processing | 5 | 0.47 | 2011 |
| Fast-squarer circuits using 3-bit-scan without overlapping bits | 0 | 0.34 | 2011 |
| Impact of Process Variations on Flip-Flops Energy and Timing Characteristics | 8 | 0.86 | 2010 |
| A new low-power high-speed single-clock-cycle binary comparator | 4 | 0.53 | 2010 |
| Impact of process variations on pulsed flip-flops: yield improving circuit-level techniques and comparative analysis | 6 | 0.50 | 2010 |
| Designing High-Speed Adders in Power-Constrained Environments | 10 | 0.77 | 2009 |
| Design And Evaluation Of An Energy-Delay-Area Efficient Datapath For Coarse-Grain Reconfigurable Computing Systems | 4 | 0.46 | 2009 |
| Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath | 8 | 0.66 | 2009 |
| An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications | 5 | 0.61 | 2009 |
| Energy Efficient Coarse-Grain Reconfigurable Array for Accelerating Digital Signal Processing | 0 | 0.34 | 2008 |
| A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation | 0 | 0.34 | 2008 |
| A matrix product accelerator for field programmable systems on chip | 10 | 0.93 | 2008 |
| A programmable carrier phase independent symbol timing recovery circuit for QPSK/OQPSK signals | 7 | 0.61 | 2008 |
| Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator | 9 | 0.97 | 2008 |
| Design and Implementation of a 90nm Low bit-rate Image Compression Core | 0 | 0.34 | 2007 |
| A New Reconfigurable Coarse-Grain Architecture for Multimedia Applications | 19 | 1.08 | 2007 |
| MORA: a new coarse-grain reconfigurable array for high throughput multimedia processing | 10 | 0.78 | 2007 |
| An efficient and optimized FPGA Feedback M-PSK Symbol Timing Recovery Architecture based on the Gardner Timing Error Detector | 1 | 0.37 | 2007 |
| Techniques for leakage energy reduction in deep submicrometer cache memories | 12 | 0.95 | 2006 |
| Leakage energy reduction techniques in deep submicron cache memories: a comparative study | 0 | 0.34 | 2006 |
| An Integrated Countermeasure Against Differential Power Analysis For Secure Smart-Cards | 13 | 1.01 | 2006 |
