Paper Info
Title
VLSI architecture for HDTV motion estimation based on block-matching algorithm
Abstract
A systolic array architecture based on an efficient data-flow management for implementing the full-search block-matching algorithm for HDTV motion estimation is described. It is capable of treating (16×16)-blocks, with a displacement of -8/+7 pixels. Serial data inputs save the pin counts and all the input data in current frame are read only once to keep the requirements to external units to a minimum. A simplified PE design reduces the computation to 1/3 of that by directly implementing the original algorithm without any influence on the performance. Simulation results show that pixel rates at about 150 MHz can be reached with 0.8 μm CMOS technology. Owing to the highly regular and modular properties, the proposed architecture is suitable for VLSI implementation. Transistor count is estimated about 320,000, which shows that the architecture can be realized in a single chip
Year
DOI
Venue
1994
10.1109/ICVD.1994.282704
VLSI Design
Keywords
Field
DocType
systolic array architecture,cmos integrated circuits,image coding,0.8 mum,pixel difference classification algorithm,vlsi architecture,serial data inputs,digital signal processing chips,motion estimation,pixel rates,cmos technology,vlsi,image sequences,simplified pe design,systolic arrays,data-flow management,digital image sequence processing,high definition television,block-matching algorithm,television coding,image processing equipment,hdtv motion estimation,bandwidth,computer architecture,data flow,computational modeling,block matching algorithm,very large scale integration,microelectronics,systolic array,chip
Transistor count,Block-matching algorithm,Computer science,Systolic array,Electronic engineering,Chip,Real-time computing,CMOS,Pixel,Motion estimation,Very-large-scale integration
Conference
ISSN
Citations 
PageRank 
1063-9667
2
0.42
References 
Authors
3
3
Name
Order
Citations
PageRank
Feng-ming Yang120.76
Stefan Wolter222.11
Rainer Laur324135.65