Title
A Flexible Parallel Simulator for Networks-on-Chip With Error Control
Abstract
This paper presents a flexible parallel simulator to evaluate the impact of different error control methods on the performance and energy consumption of networks-on-chip (NoCs). Various error control schemes can be inserted into the simulator in a plug-and-play manner for evaluation. Moreover, a highly tunable fault injection feature is developed for modeling various fault injection scenarios, including different fault injection rates, fault types, fault injection locations, and faulty flit types. Case studies performed in the proposed flexible simulation environment are presented to demonstrate the impact of a set of error control schemes on NoC performance and energy in different noise scenarios. This paper also uses the simulator to provide design guidelines for NoCs with error control capabilities.
Year
DOI
Venue
2010
10.1109/TCAD.2009.2034353
IEEE Trans. on CAD of Integrated Circuits and Systems
Keywords
DocType
Volume
tunable fault injection feature,various error control scheme,fault injection rate,error control scheme,different fault injection rate,faulty flit type,fault tolerance,networks-on-chip,various fault injection scenario,different error control method,flexible parallel simulator,fault injection feature,fault injection location,logic design,simulator,reliability,error control capability,Error control,error control,NoC,fault type,network-on-chip,different noise scenario,performance analysis and design aid
Journal
29
Issue
ISSN
Citations 
1
0278-0070
3
PageRank 
References 
Authors
0.41
20
2
Name
Order
Citations
PageRank
Qiaoyan Yu117428.58
Paul Ampadu228528.55