| RS-Mask: Random Space Masking as an Integrated Countermeasure against Power and Fault Analysis | 0 | 0.34 | 2020 |
| SCAUL: Power Side-Channel Analysis With Unsupervised Learning | 3 | 0.42 | 2020 |
| FIMA - Fault Intensity Map Analysis. | 2 | 0.40 | 2019 |
| Approximate Memory with Approximate DCT | 0 | 0.34 | 2019 |
| Enabling Approximate Storage through Lossy Media Data Compression | 0 | 0.34 | 2019 |
| Approximate Communication Strategies for Energy-Efficient and High Performance NoC: Opportunities and Challenges | 1 | 0.36 | 2019 |
| An Asymmetric Dual Output On-Chip DC-DC Converter for Dynamic Workloads | 0 | 0.34 | 2019 |
| Fault Intensity Map Analysis with Neural Network Key Distinguisher | 0 | 0.34 | 2019 |
| A Novel Single-Input-Multiple-Output DC/DC Converter for Distributed Power Management in Many-Core Systems | 0 | 0.34 | 2019 |
| An Energy-Efficient NoC Router with Adaptive Fault-Tolerance Using Channel Slicing and On-Demand TMR. | 0 | 0.34 | 2018 |
| Reconfigurable Clock Generator with Wide Frequency Range and Single-Cycle Phase and Frequency Switching | 0 | 0.34 | 2018 |
| Improving Scalability in Thermally Resilient Hybrid Photonic-Electronic NoCs | 0 | 0.34 | 2017 |
| Thermal-Aware Adaptive Fault-Tolerant Routing for Hybrid Photonic-Electronic NoC. | 2 | 0.38 | 2016 |
| Energy-efficient NoC with variable channel width | 2 | 0.37 | 2015 |
| A compact low-power eDRAM-based NoC buffer | 2 | 0.42 | 2015 |
| Breaking the energy barrier in fault-tolerant caches for multicore systems | 5 | 0.41 | 2013 |
| Variation-tolerant cache by two-layer error control codes | 2 | 0.41 | 2013 |
| Addressing network-on-chip router transient errors with inherent information redundancy | 6 | 0.45 | 2013 |
| Fine-grained splitting methods to address permanent errors in Network-on-Chip links | 5 | 0.40 | 2012 |
| Transient Error Management For Partially Adaptive Router In Network-On-Chip (Noc) | 0 | 0.34 | 2012 |
| Exploiting Programmable Temperature Compensation Devices to Manage Temperature-Induced Delay Uncertainty | 5 | 0.74 | 2012 |
| Reliable Ultra-Low-Voltage Cache Design for Many-Core Systems | 8 | 0.51 | 2012 |
| Hybrid OTDM and WDM for multicore optical communication | 0 | 0.34 | 2012 |
| Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip | 8 | 0.49 | 2012 |
| Dual-layer adaptive error control for network-on-chip links | 11 | 0.57 | 2012 |
| A Comphrehensive Networks-on-Chip Simulator for Error Control Explorations | 0 | 0.34 | 2011 |
| A Sensor System to Detect Positive and Negative Current-Temperature Dependences | 5 | 0.53 | 2011 |
| Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration | 14 | 0.65 | 2011 |
| A Dual-Layer Method for Transient and Permanent Error Co-Management in NoC Links | 6 | 0.44 | 2011 |
| A Flexible Parallel Simulator for Networks-on-Chip With Error Control | 3 | 0.41 | 2010 |
| Exploiting Parity Computation Latency for On-Chip Crosstalk Reduction | 2 | 0.37 | 2010 |
| Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip | 19 | 0.66 | 2010 |
| Error control integration scheme for reliable NoC | 8 | 0.51 | 2010 |
| Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design | 4 | 0.45 | 2010 |
| Error control combining Hamming and product codes for energy efficient nanoscale on-chip interconnects | 2 | 0.40 | 2010 |
| Self-adaptive system for addressing permanent errors in on-chip interconnects | 38 | 1.01 | 2010 |
| A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits | 6 | 1.01 | 2009 |
| Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links | 3 | 0.46 | 2009 |
| A simulator for ballistic nanostructures in a 2-D electron gas | 2 | 0.51 | 2009 |
| On Hamming Product Codes With Type-II Hybrid ARQ for On-Chip Interconnects | 30 | 0.93 | 2009 |
| Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects | 6 | 0.50 | 2009 |
| Ballistic deflection transistors and the emerging nanoscale era | 2 | 0.77 | 2009 |
| Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip | 0 | 0.34 | 2009 |
| An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n | 16 | 1.06 | 2009 |
| Adaptive error control for nanometer scale network-on-chip links | 3 | 0.38 | 2009 |
| Configurable error correction for multi-wire errors in switch-to-switch SOC links | 1 | 0.36 | 2008 |
| A Multi-Wire Error Correction Scheme For Reliable And Energy Efficient Soc Links Using Hamming Product Codes | 2 | 0.44 | 2008 |
| Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates | 6 | 0.58 | 2008 |
| Adaptive Delay Correction for Runtime Variation in Dynamic voltage Scaling Systems | 4 | 0.52 | 2008 |
| A Low-Power Safety Mode for Variation Tolerant Systems-on-Chip | 2 | 0.44 | 2008 |
