Name
Title | ||
|---|---|---|
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation |
Abstract | ||
|---|---|---|
This paper presents a compact, low power, and low jitter dual-loop injection-locked PLL with synthesizable all-digital background calibration system for clock generation. Implemented in a 65nm CMOS process, this work demonstrates a 0.7-ps RMS jitter at 1.2 GHz while having 0.97-mW power consumption resulting in an FOM of -243dB. It also consumes an area of only 0.022mm2 resulting in the best performance-area trade-off system presented up-to-date. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ASPDAC.2014.6742854 | ASP-DAC |
Keywords | Field | DocType |
all-digital background calibration system,cmos process,calibration,size 65 nm,digital phase locked loops,compact low power dual-loop injection-locked pll,low-power electronics,time 0.7 ps,clocks,fom,low jitter dual-loop injection-locked pll,cmos digital integrated circuits,performance-area trade-off system,power 0.97 mw,frequency 1.2 ghz,on-chip clock generation,low power electronics | Dual loop,Phase-locked loop,Computer science,Injection locked,Real-time computing,Electronic engineering,Cmos process,Jitter,Calibration,Low-power electronics,Power consumption | Conference |
ISSN | Citations | PageRank |
2153-6961 | 1 | 0.35 |
References | Authors | |
1 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei Deng | 1 | 28 | 3.76 |
| Ahmed Musa | 2 | 52 | 4.50 |
| Teerachot Siriburanon | 3 | 149 | 21.47 |
| Masaya Miyahara | 4 | 165 | 32.68 |
| Kenichi Okada | 5 | 497 | 100.11 |
| Akira Matsuzawa | 6 | 465 | 88.10 |