Teerachot Siriburanon

Author Info

Name	Affiliation	Papers
TEERACHOT SIRIBURANON	Tokyo Inst Technol, Dept Phys Elect, Meguro Ku, Tokyo 1528552, Japan	45
Collaborators	Citations	PageRank
96	149	21.47
Referers	Referees	References
411	481	156

Search Limit

100481

Publications (45 rows)

Collaborators (96 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking	1	0.35	2022
A Compact 0.2–0.3-V Inverse-Class-F<sub>23</sub> Oscillator for Low 1/<italic>f</italic><sup>3</sup> Noise Over Wide Tuning Range	1	0.35	2022
A Type-II Phase-Tracking Receiver	3	0.51	2021
Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS	1	0.35	2021
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL	1	0.36	2021
A 24–31 GHz Reference Oversampling ADPLL Achieving FoM<inf>jitter−N</inf> of -269.3 dB	0	0.34	2021
Oscillator Flicker Phase Noise: A Tutorial	4	0.40	2021
A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS	0	0.34	2021
Position-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K	0	0.34	2020
Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process	0	0.34	2020
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM.	0	0.34	2020
A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS	2	0.37	2019
A 31- $\mu$ W, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS	5	0.42	2019
A 0.3V, 35% Tuning-Range, 60kHz 1/f<sup>3</sup>-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoM<inf>T</inf> of -199dB in 28-nm CMOS	0	0.34	2019
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization	0	0.34	2019
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance	3	0.41	2019
A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip	1	0.36	2019
28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications	0	0.34	2019
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators.	4	0.47	2019
16.1 A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS	1	0.41	2019
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS.	2	0.36	2018
A 28-Ghz Fractional-N Frequency Synthesizer With Reference And Frequency Doublers For 5g Mobile Communications In 65nm Cmos	0	0.34	2018
A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path.	0	0.34	2018
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS	0	0.34	2017
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay.	5	0.77	2017
A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner.	0	0.34	2017
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance.	1	0.39	2017
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay.	2	0.44	2016
An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection	0	0.34	2016
A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad.	11	0.83	2016
An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB.	0	0.34	2016
25.2 A 2.2GHz −242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture	8	0.64	2015
An HDL-synthesized gated-edge-injection PLL with a current output DAC	0	0.34	2015
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection	1	0.35	2015
A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator Using Self-Adjusting Replica Bias Circuit	0	0.34	2015
14.1 A 0.048mm2 3mW synthesizable fractional-N PLL with a soft injection-locking technique	0	0.34	2015
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique	37	1.87	2015
A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular.	3	0.49	2015
A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration	29	1.67	2014
A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation	1	0.35	2014
A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits	0	0.34	2014
A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs	4	0.52	2013
A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers	17	1.26	2013
A 20 Ghz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique For A 60 Ghz Frequency Synthesizer	0	0.34	2013
A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers	1	0.36	2012