Paper Info
Title
An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions
Abstract
Current superscalar processors use a Reorder Buffer (ROB) to support speculation, precise exceptions, and reg- ister reclamation. Instructions are retired from this struc- ture in program order, which may lead to significant perfor- mance degradation if a long latency operation blocks the ROB head. In this paper, a checkpoint-free out-of-order commit architecture is proposed, which replaces the ROB with a small structure called Validation Buffer (VB) from which instructions are retired as soon as their speculative state is resolved. An aggressive register reclamation mech- anism targeted to this microarchitecture is also devised. Ex- perimental results show that the VB microarchitecture is much more efficient than a ROB-based microprocessor. For example, a 32-entry VB provides similar performance to a 256-entry ROB, while reducing the utilization of other ma- jor processor structures.
Year
DOI
Venue
2009
10.1109/DSD.2009.237
DSD
Keywords
Field
DocType
buffer circuits,microprocessor chips,ROB-based microprocessor,checkpoint-free out-of-order commit architecture,out-of-order instruction retirement,register reclamation,register reclamation mechanism,superscalar reorder buffer processors,validation buffer
Speculation,Latency (engineering),Computer science,Real-time computing,Out-of-order execution,Re-order buffer,Microarchitecture,Commit,Parallel computing,Microprocessor,Superscalar,Operating system,Embedded system
Conference
Citations 
PageRank 
References 
1
0.35
13
Authors
5
Name
Order
Citations
PageRank
Salvador Petit115327.28
Rafael Ubal232216.93
Julio Sahuquillo342053.71
Pedro Lopez438727.39
Jose Duato589354.65