Name
Abstract | ||
|---|---|---|
A Cellular Neural Network (CNN) is a highly-parallel, analog processor that can significantly outperform von Neumann architectures for certain classes of problems. Here, we show how emerging, beyond-CMOS devices could help to further enhance the capabilities of CNNs, particularly for solving problems with non-binary outputs. We show how CNNs based on devices such as graphene transistors -- with multiple steep current growth regions separated by negative differential resistance (NDR) in their I-V characteristics -- could be used to recognize multiple patterns simultaneously. (This would require multiple steps given a conventional, binary CNN.) Also, we demonstrate how tunneling field effect transistors (TFETs) can be used to form circuits capable of performing similar tasks. With this approach, more \"exotic\" device I-V characteristics are not required -- which should be an asset when considering issues such as cell-to-cell mismatch, etc. As a case study, we present a CNN-cell design that employs TFET-based circuitry to realize ternary outputs. We then illustrate how this hardware could be employed to efficiently solve a tactile sensing problem. The total number of computation steps as well as the required hardware could be reduced significantly when compared to an approach based on a conventional CNN. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.7873/DATE.2014.150 | DATE |
Keywords | Field | DocType |
CMOS integrated circuits,cellular neural nets,electronic engineering computing,field effect transistors,graphene,negative resistance,tunnel transistors,CMOS devices,I-V characteristics,NDR,TFETs,analog processor,binary CNN,cellular neural network,exotic device,graphene transistors,multiple steep current growth regions,negative differential resistance,nonbinary outputs,nonvon Neumann architectures,steep-slope transistors,tactile sensing problem,ternary outputs,tunneling field effect transistors | Field-effect transistor,Computer science,Electronic engineering,CMOS,Transistor,Electronic circuit,Cellular neural network,Von Neumann architecture,Binary number,Computation | Conference |
ISSN | Citations | PageRank |
1530-1591 | 2 | 0.39 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Indranil Palit | 1 | 57 | 6.28 |
| Behnam Sedighi | 2 | 58 | 10.33 |
| András Horváth | 3 | 350 | 37.22 |
| Xiaobo Sharon Hu | 4 | 2004 | 208.24 |
| Joseph Nahas | 5 | 68 | 21.60 |
| Michael Niemier | 6 | 191 | 31.85 |