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JOSEPH NAHAS
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Name
Affiliation
Papers
JOSEPH NAHAS
University of Notre Dame, Notre Dame, IN
15
Collaborators
Citations
PageRank
35
68
21.60
Referers
Referees
References
206
261
107
Search Limit
100
261
Publications (15 rows)
Collaborators (35 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Can beyond-CMOS devices illuminate dark silicon?
4
0.42
2018
Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits.
6
0.47
2016
TFET-based Operational Transconductance Amplifier Design for CNN Systems
3
0.39
2015
Analog Circuit Design Using Tunnel-FETs
12
0.76
2015
Analytically Modeling Power and Performance of a CNN System
1
0.35
2015
A CNN-inspired mixed signal processor based on tunnel transistors
0
0.34
2015
Architectural impacts of emerging transistors
3
0.41
2014
Design of 3D nanomagnetic logic circuits: A full-adder case study
1
0.40
2014
Impact of steep-slope transistors on non-von neumann architectures: CNN case study
2
0.39
2014
Cellular neural networks for image analysis using steep slope devices
3
0.43
2014
Nontraditional Computation Using Beyond-CMOS Tunneling Devices
1
0.36
2014
Systematic design of nanomagnet logic circuits
1
0.44
2013
Making non-volatile nanomagnet logic non-volatile
1
0.44
2012
A 180 Kbit Embeddable MRAM Memory Module
1
0.75
2008
A 4-Mb 0.18-/spl mu/m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers
29
15.25
2005
1