Name
Abstract | ||
|---|---|---|
Systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are pre-designed and pre-verified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early design decisions regarding performance, area, timing and power; and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1145/944645.944687 | CODES+ISSS |
Keywords | Field | DocType |
computer architecture,integrated circuit layout,system-on-chip,systems analysis,timing,IP characterization data,SEAS,chip area,core selection,cross-domain effect,design analysis,design space exploration,floorplanning,front-end design,intellectual property,system analysis,system for early analysis of SoCs,systems-on-chip,timing | Integrated circuit layout,Architecture,System on a chip,Computer science,Reuse,Systems analysis,Real-time computing,Chip,Design space exploration,Embedded system,Floorplan | Conference |
ISBN | Citations | PageRank |
1-58113-742-7 | 10 | 1.38 |
References | Authors | |
9 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Reinaldo A. Bergamaschi | 1 | 420 | 52.57 |
| Youngsoo Shin | 2 | 836 | 93.86 |
| Nagu Dhanwada | 3 | 163 | 12.45 |
| Subhrajit Bhattacharya | 4 | 462 | 36.93 |
| William E. Dougherty | 5 | 64 | 5.96 |
| Indira Nair | 6 | 143 | 23.45 |
| John Darringer | 7 | 10 | 2.06 |
| Sarala Paliwal | 8 | 21 | 2.47 |