Name
Abstract | ||
|---|---|---|
Asynchronous logic is a promising technology for building the chip-level interconnect of multi-core systems. However, asynchronous circuits are vulnerable to faults. This paper presents a novel scheme to improve the robustness of asynchronous systems. Our first contribution is a fault tolerant delay-insensitive redundant check coding scheme named DIRC. Using DIRC in 4-phase 1-of-n quasi-delay-insensitive (QDI) interconnects, all 1-bit and some multi-bit transient faults can be tolerated. The DIRC and the basic 4-phase 1-of-n pipeline stages are mutually exchangeable so that arbitrary basic stages can be replaced by DIRC stages to strengthen the fault-tolerance of long wires. Our second contribution, RPA, is a redundant technique to protect the acknowledge wires from transient faults - an issue that has long been disregarded by the community. The DIRC pipelines (using DIRC plus RPA) were simulated using the UMC 0.13μm standard cell library and compared with the basic pipelines. Detailed experimental results show that the 128-bit DIRC 1-of-4 pipeline is only 13% slower than the basic one but increases fault-tolerance hundred-folds when multi-bit transient faults are considered. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/DSD.2013.11 | DSD |
Keywords | Field | DocType |
word length 128 bit,integrated circuit interconnections,basic pipeline,asynchronous interconnects,multi-bit transient fault,multicore systems,dirc stage,fault tolerant computing,chip-level interconnection,asynchronous circuit,transient fault tolerant qdi interconnects,redundant check code,asynchronous system,fault tolerance,128-bit dirc,asynchronous logic,multiprocessing systems,4-phase 1-of-n quasidelay-insensitive interconnects,asynchronous systems,transient fault,multibit transient faults,dirc pipeline,dirc 1-of-4 pipeline,redundancy,1-bit transient faults,transient fault tolerant qdi,fault tolerant delay-insensitive redundant check coding scheme,asynchronous circuits,transient faults,size 0.13 mum,quasi-delay-insensitive circuits,arbitrary basic stage,pipeline processing | Asynchronous communication,Computer science,Parallel computing,Robustness (computer science),Real-time computing,Redundancy (engineering),Fault tolerance,Standard cell,Electronic circuit,Interconnection,Asynchronous circuit | Conference |
Citations | PageRank | References |
3 | 0.43 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guangda Zhang | 1 | 11 | 3.63 |
| Wei Song | 2 | 17 | 1.93 |
| Jim D. Garside | 3 | 350 | 33.15 |
| Javier Navaridas | 4 | 201 | 23.58 |
| Zhi-Ying Wang | 5 | 870 | 127.04 |