| On the routing and scalability of MZI-based optical Beneš interconnects | 0 | 0.34 | 2021 |
| Relating the Bisection Width of Dual-Port, Server-Centric Datacenter Networks and the Solution of Edge Isoperimetric Problems in Graphs | 0 | 0.34 | 2020 |
| INRFlow : an interconnection networks research flow-level simulation framework. | 0 | 0.34 | 2019 |
| Enabling Standalone FPGA Computing | 0 | 0.34 | 2019 |
| Scalability analysis of optical Beneš networks based on thermally/electrically tuned Mach-Zehnder interferometers | 0 | 0.34 | 2019 |
| Enabling shared memory communication in networks of MPSoCs. | 1 | 0.37 | 2019 |
| Design Exploration of Multi-tier Interconnection Networks for Exascale Systems | 0 | 0.34 | 2019 |
| On the Effects of Allocation Strategies for Exascale Computing Systems with Distributed Storage and Unified Interconnects | 0 | 0.34 | 2019 |
| Can the Optimizer Cost be Used to Predict Query Execution Times | 0 | 0.34 | 2019 |
| High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/Routings. | 2 | 0.42 | 2018 |
| Network-on-chip evaluation for a novel neural architecture | 0 | 0.34 | 2018 |
| Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development. | 2 | 0.37 | 2018 |
| Designing Low-Power, Low-Latency Networks-on-Chip by Optimally Combining Electrical and Optical Links | 6 | 0.44 | 2017 |
| Handling Physical-Layer Deadlock Caused by Permanent Faults in Quasi-Delay-Insensitive Networks-on-Chip. | 0 | 0.34 | 2017 |
| Improved routing algorithms in the dual-port datacenter networks HCN and BCN. | 2 | 0.36 | 2017 |
| The stellar transformation: From interconnection networks to datacenter networks. | 0 | 0.34 | 2017 |
| A Survey on Optical Network-on-Chip Architectures. | 4 | 0.40 | 2017 |
| On the Effects of Data-Aware Allocation on Fully Distributed Storage Systems for Exascale. | 0 | 0.34 | 2017 |
| The Next Generation of Exascale-Class Systems: The ExaNeSt Project | 2 | 0.39 | 2017 |
| An Optimal Single-Path Routing Algorithm in the Datacenter Network DPillar | 1 | 0.34 | 2017 |
| Subchannel Scheduling for Shared Optical On-chip Buses | 0 | 0.34 | 2017 |
| A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-Chip. | 10 | 0.46 | 2016 |
| Cyclic Power-Gating as an Alternative to Voltage and Frequency Scaling | 0 | 0.34 | 2016 |
| CHO: towards a benchmark suite for OpenCL FPGA accelerators | 5 | 0.54 | 2015 |
| Amon: An Advanced Mesh-like Optical NoC | 8 | 0.44 | 2015 |
| Project Beehive: A Hardware/Software Co-designed Stack for Runtime and Architectural Research. | 1 | 0.37 | 2015 |
| On Routing Algorithms for the DPillar Data Centre Networks. | 0 | 0.34 | 2015 |
| Star-Replaced Networks: A Generalised Class of Dual-Port Server-Centric Data Centre Networks | 0 | 0.34 | 2015 |
| Accelerating Interconnect Analysis Using High-Level HDLs and FPGA, SpiNNaker as a Case Study | 0 | 0.34 | 2015 |
| Deadlock Recovery in Asynchronous Networks on Chip in the Presence of Transient Faults | 0 | 0.34 | 2015 |
| Routing Algorithms for Recursively-Defined Data Centre Networks | 1 | 0.36 | 2015 |
| Analysis of FPGA and software approaches to simulate unconventional computer architectures | 0 | 0.34 | 2015 |
| SpiNNaker: Enhanced multicast routing | 4 | 0.42 | 2015 |
| Protecting QDI interconnects from transient faults using delay-insensitive redundant check codes. | 3 | 0.39 | 2014 |
| On generating multicast routes for SpiNNaker | 2 | 0.40 | 2014 |
| An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults | 2 | 0.37 | 2014 |
| SpiNNaker: Fault tolerance in a power- and area- constrained large-scale neuromimetic architecture | 5 | 0.56 | 2013 |
| Transient Fault Tolerant QDI Interconnects Using Redundant Check Code | 3 | 0.43 | 2013 |
| Population-based routing in the SpiNNaker neuromorphic architecture. | 8 | 0.50 | 2012 |
| Analytical Assessment of the Suitability of Multicast Communications for the SpiNNaker Neuromimetic System | 3 | 0.36 | 2012 |
| Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation | 2 | 0.37 | 2012 |
| Scalable communications for a million-core neural processing architecture | 6 | 0.66 | 2012 |
| Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System. | 9 | 0.47 | 2012 |
| Indirect cube: A power-efficient topology for compute clusters | 1 | 0.41 | 2011 |
| Simulating and evaluating interconnection networks with INSEE | 24 | 1.07 | 2011 |
| Reducing complexity in tree-like computer interconnection networks | 14 | 0.80 | 2010 |
| SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network | 7 | 0.46 | 2010 |
| Full-system simulation of distributed memory multicomputers | 2 | 0.41 | 2009 |
| Effects of Job and Task Placement on Parallel Scientific Applications Performance | 13 | 0.77 | 2009 |
| Understanding the interconnection network of SpiNNaker | 25 | 0.99 | 2009 |
