Paper Info
Title
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure
Abstract
This paper presents a new 8T (8-transistor) SRAM cell layout mitigating multiple-bit upset (MBU) in a divided wordline structure. Because bitlines along unselected columns are not activated, the divided wordline structure eliminates a half-select problem and achieves low-power operation, which is often preferred for low-power / low-voltage applications. However, the conventional 8T SRAM with the divided wordline structure engenders MBUs because all bits in the same word are physically adjoining. Consequently, error correction coding (ECC) techniques are difficult to apply. This paper presents a new 8T cell layout pattern that separates internal latches in SRAM cells using both an n-well and a p-substrate. We investigated an SEU cross section of nMOS that is 3.5-4.5 times higher than that of pMOS. Using an iRoC TFIT simulator, we confirmed that the proposed 8T cell has better neutron-induced MBU tolerance. The MBU in the proposed 8T SRAM is improved by 90.70% and the MBU soft error rate (SER) is decreased to 3.46 FIT at 0.9 V when ECC is implemented. Additionally, we conducted Synopsys 3-D TCAD simulation, which indicates that the LET threshold (LETth) in single-event upset (SEU) is also improved by 66.47% in the proposed 8T SRAM by a common-mode effect.
Year
DOI
Venue
2012
10.1109/IOLTS.2011.5993829
IEICE Transactions
Keywords
DocType
Volume
soft error,sram,alpha particle
Journal
95-C
Issue
ISSN
Citations 
10
1745-1353
2
PageRank 
References 
Authors
1.44
2
5
Name
Order
Citations
PageRank
Shusuke Yoshimoto13012.56
takuro amashita221.44
Shunsuke Okumura36312.54
hiroshi kawaguchi421.44
masahiko yoshimoto511734.06