Name
Abstract | ||
|---|---|---|
We present an Inversed Temperature Dependence (ITD) aware clock skew scheduling framework. Specifically, we demonstrate how our framework can assist dual-Vth assignment in preventing timing violations arising due to ITD effect. We formulate the ITD aware synthesis problem and prove that it is NP-Hard. Then, we propose an algorithm for synergistic temperature aware clock skew scheduling and dual-Vth assignment. Experiments on ISCAS89 benchmarks reveal that several circuits synthesized by the traditional high-temperature corner based flow with a commercial tool exhibit timing violations in the low temperature range while all circuits generated using our methodology for the same timing constraints have guaranteed timing. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/DATE.2010.5457079 | DATE |
Keywords | Field | DocType |
synergistic temperature aware clock skew scheduling,sequential circuits,dual-vth assignment,np-hard,inversed temperature dependence,itd effect,itd aware synthesis problem,itd aware synthesis,timing violation,timing constraint,sequential circuit,high-temperature corner based flow,clocks,iscas89 benchmarks,aware clock skew scheduling,logic design,circuit complexity,integrated circuit design,commercial tool exhibit timing,synergistic temperature,itd aware clock skew scheduling,low temperature range,benchmark testing,logic,logic gates,scheduling algorithm,clock skew,np hard | Logic synthesis,Timing failure,Sequential logic,Circuit complexity,Scheduling (computing),Computer science,Parallel computing,Real-time computing,Static timing analysis,Integrated circuit design,Benchmark (computing) | Conference |
ISSN | ISBN | Citations |
1530-1591 | 978-1-4244-7054-9 | 1 |
PageRank | References | Authors |
0.37 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jieyi Long | 1 | 129 | 8.98 |
| Seda Öǧrenci Memik | 2 | 488 | 42.57 |