Paper Info
Title
Bus optimization for low-power data path synthesis based on network flow method
Abstract
Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral level and RT level of design. This paper addresses the problem of minimizing power dissipated in switching of the buses in data path synthesis. Unlike the previous approaches in which minimization of the power consumed in buses has not been considered until operation scheduling is completed, our approach integrates the bus binding problem into scheduling to exploit the impact of scheduling on reduction of power dissipated on the buses more fully and effectively. We accomplish this by formulating the problem into a flow problem in a network, and devising an efficient algorithm which iteratively finds maximum flow of minimum cost solutions in the network. Experimental results on a number of benchmark problems show that given resource and global timing constraints our designs are 22% power-efficient over the designs produced by a random-move based solution, and 18% power-efficient over the designs by a clock-step based optimal solution.
Year
DOI
Venue
2000
10.1109/ICCAD.2000.896491
ICCAD
Keywords
Field
DocType
sub-micron feature size,low-power data path synthesis,network flow method,rt level,minimum cost solution,operation scheduling,flow problem,maximum flow,bus optimization,optimal solution,behavioral level,benchmark problem,bus binding problem,power dissipation,binding problem,inductance,power efficiency,vlsi,network flow,high level synthesis
Flow network,Mathematical optimization,Inductance,Scheduling (computing),Computer science,High-level synthesis,Real-time computing,Electronic engineering,Minification,Maximum flow problem,Very-large-scale integration,Binding problem
Conference
ISBN
Citations 
PageRank 
0-7803-6448-1
14
0.66
References 
Authors
10
2
Name
Order
Citations
PageRank
Sungpack Hong186433.20
Taewhan Kim21087113.31