Name
Affiliation
Papers
SUNGPACK HONG
Pervasive Parallelism Laboratory, Stanford University, USA
30
Collaborators
Citations 
PageRank 
69
864
33.20
Referers 
Referees 
References 
2193
885
391
Search Limit
1001000
Title
Citations
PageRank
Year
TurboFlux: A Fast Continuous Subgraph Matching System for Streaming Graph Data.50.402018
PGX.D/Async: A Scalable Distributed Graph Pattern Matching Engine.20.382017
Modeling, analysis, and experimental comparison of streaming graph-partitioning policies.60.422017
A Balanced Parallel Distributed Sorting Implemented with PGX.D.00.342016
PGQL: a property graph query language.190.642016
Using Domain-Specific Languages For Analytic Graph Databases.40.422016
ASGraph: a mutable multi-versioned graph container with high analytical performance.10.352016
PGX.D: a fast distributed graph processing engine310.792015
Memory fast-forward: a low cost special function unit to enhance energy efficiency in GPU for big data processing20.362015
A scalable processing-in-memory accelerator for parallel graph processing1773.812015
Taming Subgraph Isomorphism for RDF Query Processing200.622015
PGX.ISO: Parallel and Efficient In-Memory Engine for Subgraph Isomorphism70.522014
Fast In-Memory Triangle Listing for Large Real-World Graphs100.492014
Simplifying Scalable Graph Processing with a Domain-Specific Language160.652014
On fast parallel detection of strongly connected components (SCC) in small-world graphs331.002013
Graph analysis: do we have to reinvent the wheel?150.882013
Early experiences in using a domain-specific language for large-scale graph analysis30.412013
Green-Marl: a DSL for easy and efficient graph analysis1194.032012
A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware10.352012
Efficient Parallel Graph Exploration on Multi-Core CPU and GPU1304.602011
Accelerating CUDA graph algorithms at maximum warp1715.872011
Eigenbench: A simple exploration tool for orthogonal TM characteristics310.992010
FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures80.662010
Dynamic voltage scaling of supply and body bias exploiting software runtime distribution120.812008
A systematic IP and bus subsystem modeling for platform-based system design20.462006
Runtime distribution-aware dynamic voltage scaling90.652006
Creation and utilization of a virtual platform for embedded software optimization:: an industrial case study70.602006
Bus Optimization for Low Power in High-Level Synthesis10.482003
Bus optimization for low-power data path synthesis based on network flow method140.662000
Decomposition of Bus-Invert Coding for Low-Power I/O.80.562000