Name
Abstract | ||
|---|---|---|
Scan based at-speed testing has become mandatory in industry to detect delay defects today in order to maintain test quality and reduce test cost. However, the effects of power supply droop during test application often introduce timing uncertainty, such as clock stretch and additional gate delay. It leads to false failure and test escape during test and makes the application of the at-speed scan testing become a challenge task to screen out delay defects successfully. In this paper, we review existing studies about the power supply droop and the methods to reduce its impact on at-speed scan testing. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ATS.2012.63 | Asian Test Symposium |
Keywords | Field | DocType |
structural at-speed testing,challenge task,integrated circuit testing,at-speed testing,false failure,additional gate delay,timing uncertainty,test escape,test quality,structural test,power supply droop,test cost,at-speed scan testing,gate delay,clocks,fault diagnosis,clock stretch,at-speed scan test,test application,test cost reduction,delay defect detection,delay defect,test power reduction,rlc circuits,testing,switches,logic gates | Logic gate,Computer science,Test quality,Electronic engineering,Real-time computing,RLC circuit,Voltage droop | Conference |
ISSN | ISBN | Citations |
1081-7735 E-ISBN : 978-0-7695-4876-0 | 978-0-7695-4876-0 | 2 |
PageRank | References | Authors |
0.37 | 16 | 1 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xijiang Lin | 1 | 687 | 42.03 |