| On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation | 0 | 0.34 | 2021 |
| Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults | 0 | 0.34 | 2021 |
| On Generating Fault Diagnosis Patterns for Designs with X Sources | 0 | 0.34 | 2019 |
| TEA: A Test Generation Algorithm for Designs with Timing Exceptions | 0 | 0.34 | 2019 |
| Functional Broadside Test Generation Using a Commercial ATPG Tool | 0 | 0.34 | 2017 |
| Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill. | 5 | 0.41 | 2016 |
| On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection | 0 | 0.34 | 2016 |
| On generating high quality tests based on cell functions | 4 | 0.44 | 2015 |
| On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. | 2 | 0.41 | 2015 |
| Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits | 3 | 0.39 | 2015 |
| Using dynamic shift to reduce test data volume in high-compression designs | 4 | 0.44 | 2014 |
| Multicycle-aware At-speed Test Methodology | 2 | 0.51 | 2013 |
| Test compaction for small-delay defects using an effective path selection scheme | 6 | 0.43 | 2013 |
| On Utilizing Test Cube Properties to Reduce Test Data Volume Further | 16 | 0.66 | 2012 |
| Power Supply Droop and Its Impacts on Structural At-Speed Testing | 2 | 0.37 | 2012 |
| Low power testing - What can commercial DFT tools provide? | 0 | 0.34 | 2011 |
| Power Aware Embedded Test | 4 | 0.45 | 2011 |
| Low capture power at-speed test in EDT environment. | 1 | 0.42 | 2010 |
| Detecting and diagnosing open defects | 0 | 0.34 | 2010 |
| Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains | 2 | 0.40 | 2010 |
| On reducing scan shift activity at RTL | 1 | 0.36 | 2010 |
| Adaptive Low Shift Power Test Pattern Generator for Logic BIST | 7 | 0.59 | 2010 |
| Test Generation for Designs with On-Chip Clock Generators | 8 | 0.68 | 2009 |
| Low-power scan operation in test compression environment | 31 | 0.91 | 2009 |
| Test Generation for Interconnect Opens | 11 | 0.74 | 2008 |
| Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells | 16 | 0.73 | 2008 |
| Test Power Reduction by Blocking Scan Cell Outputs | 13 | 0.94 | 2008 |
| Reducing Scan Shift Power at RTL | 4 | 0.46 | 2008 |
| Scan-Based Tests with Low Switching Activity | 15 | 1.07 | 2007 |
| Low Shift and Capture Power Scan Tests | 33 | 1.34 | 2007 |
| Preferred Fill: A Scalable Method To Reduce Capture Power For Scan Based Designs | 150 | 4.32 | 2006 |
| Scan Tests with Multiple Fault Activation Cycles for Delay Faults | 16 | 0.90 | 2006 |
| The Impacts of Untestable Defects on Transition Fault Testing | 3 | 0.51 | 2006 |
| Propagation delay fault: a new fault model to test delay faults | 3 | 0.46 | 2005 |
| Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study | 7 | 0.63 | 2005 |
| Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality | 21 | 1.10 | 2005 |
| High-Frequency, At-Speed Scan Testing | 76 | 5.03 | 2003 |
| Test generation for designs with multiple clocks | 32 | 1.34 | 2003 |
| Conflict driven techniques for improving deterministic test pattern generation | 17 | 0.72 | 2002 |
| Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture | 21 | 2.47 | 2002 |
| Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan | 1 | 0.62 | 2001 |
| On static test compaction and test pattern ordering for scan designs | 37 | 3.06 | 2001 |
| SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration | 16 | 0.67 | 2000 |
| Techniques for improving the efficiency of sequential circuit test generation | 24 | 0.88 | 1999 |
| Full scan fault coverage with partial scan | 19 | 0.74 | 1999 |
| Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits | 7 | 0.57 | 1999 |
| MIX: A Test Generation System for Synchronous Sequential Circuits | 22 | 1.09 | 1998 |
| On Finding Undetectable and Redundant Faults in Synchronous Sequential Circuits | 25 | 1.06 | 1998 |
