Name
Abstract | ||
|---|---|---|
This paper describes first a half-rate, 2.5-V, 1.4-W, 87-Gb/s transmitter with on-chip PLL fabricated in a production 130-nm SiGe BiCMOS process. Next, the most critical blocks required for die implementation of a full-rate 100-Gb/s serial transceiver are explored. State-of-the art 105-GHz, SiGe HBT static frequency dividers and VCOs operating from 2.5-V supply, as well as 65-nm CMOS, 1.2-V, 90-GHz static frequency dividers, low-phase noise VCOs, and 100-GHz clock distribution network amplifiers are fully characterized over power supply and process spread, and over temperature up to 100 degrees C. Inductor and transformer modeling and scaling beyond 200 GHz; in nanoscale CMOS and SiGe BiCMOS technologies, are also described. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/CICC.2007.4405776 | PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE |
Keywords | Field | DocType |
phase locked loops,chip,phase noise,transceivers | Transmitter,Phase-locked loop,BiCMOS,Transceiver,Computer science,Phase noise,Inductor,Electronic engineering,CMOS,Electrical engineering,Amplifier | Conference |
Citations | PageRank | References |
3 | 3.04 | 3 |
Authors | ||
9 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sorin P. Voinigescu | 1 | 221 | 53.57 |
| Ricardo Andres Aroca | 2 | 48 | 10.32 |
| Timothy O. Dickson | 3 | 141 | 22.86 |
| Sean T. Nicolson | 4 | 103 | 17.97 |
| Theodoros Chalvatzis | 5 | 19 | 6.03 |
| P. Chevalier | 6 | 540 | 50.49 |
| Patrice Garcia | 7 | 32 | 7.18 |
| Christophe Gamier | 8 | 5 | 3.49 |
| Bernard Sautreuil | 9 | 53 | 9.88 |