Name
Abstract | ||
|---|---|---|
In this communication, an ultra-compact I-V nanometer MOS model is used to predict the dynamic characteristics (propagation delay and rise/fall times) of CMOS inverter and more complex stacked-transistor gates. Simulations reveal typical errors within 1-3% (always less than 6%) for the simple inverter case and within 4-8% (always less than 11%) in the case of stacked-transistor gates. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCAS.2012.6272018 | ISCAS |
Keywords | Field | DocType |
CMOS digital integrated circuits,invertors,logic design,logic gates,nanotechnology,CMOS inverter,logic gates dynamic modeling,propagation delay,stacked-transistor gates,ultra-compact I-V nanometer MOS model,ultra-compact MOS model | Inverter,Logic gate,Digital electronics,NMOS logic,Pass transistor logic,Computer science,AND-OR-Invert,CMOS,Electronic engineering,Logic family,Electrical engineering | Conference |
ISSN | Citations | PageRank |
0271-4302 | 0 | 0.34 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Elio Consoli | 1 | 117 | 11.62 |
| Gianluca Giustolisi | 2 | 50 | 14.17 |
| Gaetano Palumbo | 3 | 708 | 106.77 |