| Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior | 0 | 0.34 | 2021 |
| Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints | 0 | 0.34 | 2021 |
| In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers | 0 | 0.34 | 2019 |
| Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area. | 2 | 0.37 | 2019 |
| Bessel-like compensation of three-stage operational transconductance amplifiers. | 0 | 0.34 | 2018 |
| Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017. | 0 | 0.34 | 2018 |
| Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes | 3 | 0.55 | 2015 |
| Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time | 1 | 0.35 | 2015 |
| Monolithic quenching-and-reset circuit for single-photon avalanche diodes | 0 | 0.34 | 2014 |
| A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers | 1 | 0.63 | 2013 |
| Logic gates dynamic modeling by means of an ultra-compact MOS model. | 0 | 0.34 | 2012 |
| Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators | 14 | 0.83 | 2012 |
| An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits. | 19 | 1.56 | 2012 |
| Verilog-A Modeling Of Spad Statistical Phenomena | 1 | 0.41 | 2011 |
| Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model | 0 | 0.34 | 2011 |
| An ultra-compact MOS model in nanometer technologies | 0 | 0.34 | 2011 |
| Low-voltage LDO Compensation Strategy based on Current Amplifiers | 2 | 0.53 | 2008 |
| Modeling of EMI propagation in switched-capacitor ΣΔ A/D converter | 0 | 0.34 | 2008 |
| Resistance of Feedback Amplifiers: A Novel Representation | 0 | 0.34 | 2007 |
| High-Drive and Linear CMOS Class-AB Pseudo-Differential Amplifier | 3 | 0.59 | 2007 |
| Two-Stage Ota Design Based On Settling-Time Constraints | 0 | 0.34 | 2007 |
| Analysis Of Power Supply Gain Of Cmos Bandgap References | 0 | 0.34 | 2006 |
| NMOS Low Drop-Out Regulator with Dynamic Biasing | 1 | 0.40 | 2006 |
| Analysis and optimization of a low-voltage class-AB output stage. | 0 | 0.34 | 2005 |
| Comparison of methods for predicting distortion in class-AB stages. | 0 | 0.34 | 2005 |
| Sigma-Delta A/D fuzzy converter | 0 | 0.34 | 2004 |
| CMOS implementation of an extended CNN cell to deal with complex dynamics | 0 | 0.34 | 2003 |
| Analysis of power supply noise attenuation in a PTAT current source | 0 | 0.34 | 2002 |
| Detailed frequency analysis of power supply rejection in Brokaw bandgap | 2 | 1.11 | 2001 |
| High-linear class AB transconductor for high-frequency applications | 1 | 0.43 | 2000 |
| A 1.5 V CMOS voltage multiplier | 0 | 0.34 | 1998 |
