Name
Title | ||
|---|---|---|
A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique |
Abstract | ||
|---|---|---|
Compute intensive signal Processing Algorithms demand efficient execution of high performance arithmetic operations. Since, double base number system (DBNS) offers high performance arithmetic units, it is gaining attention to many researchers .However, the advantage of DBNS can not be exploited due to large conversion time from binary to DBNS. Keeping this issue in view, this paper presents a novel conversion scheme using parallel search technique. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1145/2093339.2093343 | SIGARCH Computer Architecture News |
Keywords | Field | DocType |
double base number system,high performance arithmetic operation,intensive signal,efficient execution,large conversion time,new architecture,parallel search technique,novel conversion scheme,high performance arithmetic unit,binary search tree,signal processing,indexation,look up table | Lookup table,Architecture,Computer science,Parallel search,Base Number,Parallel computing,Field-programmable gate array,Real-time computing,Binary search tree,Signal processing algorithms,Binary number | Journal |
Volume | Issue | Citations |
39 | 5 | 0 |
PageRank | References | Authors |
0.34 | 4 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Satrughna Singha | 1 | 0 | 1.01 |
| Aniruddha Ghosh | 2 | 140 | 11.32 |
| Amitabha Sinha | 3 | 14 | 7.00 |