Amitabha Sinha - Citegraph

Author Info

Name	Affiliation	Papers
AMITABHA SINHA	West Bengal University of Technology, Salt Lake, Kolkata, India	19
Collaborators	Citations	PageRank
17	14	7.00
Referers	Referees	References
45	144	93

Search Limit

100144

Publications (19 rows)

Collaborators (17 rows)

Referers (45 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Field Programmable DSP Arrays - A	0	0.34	2013
A novel reconfigurable architecture of a DSP processor for efficient mapping of DSP functions using field programmable DSP arrays	0	0.34	2013
High performance MAC unit for DSP and cryptographic applications	0	0.34	2013
An integrated development platform of a reconfigurable radio processor for software defined radio	0	0.34	2013
Design and simulation of MAC unit using combinational circuit and adder	0	0.34	2013
Performance analysis of a FPGA based novel binary and DBNS multiplier	0	0.34	2013
High efficiency MAC unit used in digital signal processing and elliptic curve cryptography	0	0.34	2013
FPGA implementation of a novel DCT architecture reducing constant cosine terms	0	0.34	2013
FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT	0	0.34	2012
Design of a Reconfigurable DSP Processor with Bit Efficient Residue Number System	1	0.36	2012
A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system	0	0.34	2012
A new algorithm for computing triple-base number system	0	0.34	2012
A Scheme for Improving Bit Efficiency for Residue Number System.	2	0.37	2012
"Floating point RNS": a new concept for designing the MAC unit of digital signal processor	0	0.34	2012
High speed residue number system (RNS) based FIR filter using distributed arithmetic (DA)	4	0.53	2011
A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique	0	0.34	2011
Conversion of binary to single-term triple base numbers for DSP applications	0	0.34	2011
A novel architecture for conversion of binary to single digit double base numbers	5	0.61	2010
An FPGA Based Architecture of a Novel Reconfigurable Radio Processor for Software Defined Radio	2	0.39	2009

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