Name
Abstract | ||
|---|---|---|
In this paper a new method for reducing scan shift is presented. Scan design is one of the most popular design for test technology for sequential circuits. However it requires much test application time and test data when applied for circuits with many flip-flops. The new scan method utilizes two configuration of scan chains, a folding scan tree and a fully compatible scan tree. Using test pattern including many don't care values are used to configure a fully compatible scan tree in order to reduce scan shift without degrading fault coverage. And then a folding scan tree is configured to reduce the length of scan chain to reduce scan shift. Experimental results for benchmark circuits shows this scan method can reduce many scan shifts. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ATS.2003.1250772 | Asian Test Symposium |
Keywords | Field | DocType |
boundary scan testing,design for testability,logic design,logic testing,compatible scan tree,design for test,fault coverage,flip-flops,folding scan trees,scan chain length reduction,scan shift reduction,sequential circuits,test application time,test pattern don't care values | Logic synthesis,Boundary scan,Design for testing,Sequential logic,Fault coverage,Computer science,Algorithm,Scan chain,Real-time computing,Electronic engineering,Test data,Test compression | Conference |
Citations | PageRank | References |
12 | 0.87 | 7 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Yotsuyanagi | 1 | 70 | 19.04 |
| Toshimasa Kuchii | 2 | 19 | 2.14 |
| Shigeki Nishikawa | 3 | 12 | 0.87 |
| Masaki Hashizume | 4 | 98 | 27.83 |
| Kozo Kinoshita | 5 | 756 | 118.08 |