Name
Title | ||
|---|---|---|
A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories |
Abstract | ||
|---|---|---|
3-D-stacked memory using through-silicon-vias (TSVs) has emerged as a good alternative for overcoming the limitation of 2-D memory technology. Among many issues with 3-D-stacked memory, yield is one of the major challenges for mass production. This paper proposes a new fuse architecture and redundancy scheme to improve the yield of 3-D-stacked memories. The new fuse architecture is developed based on the fact that the unused redundancies in prebond repair cause the inefficiency. Therefore, the new fuse architecture provides a way to share redundancies in prebond and postbond repairs. There are two kinds of operation modes. One is an enable mode for collecting the used redundancy information. The other is a mask mode for obtaining faulty redundancy information using a short test algorithm. Using the new fuse architecture, a new redundancy scheme called the post-share scheme is developed to achieve optimal yield. The post-share scheme allocates the fixed number of spare rows and columns for each repair just like other schemes. However, only allocated redundancies are used in prebond repair, while both the redundancies allocated for postbond repair and unused redundancies in prebond repair can be used for postbond repair. Experimental results show that the post-share redundancy scheme significantly increases the final yield of 3-D-stacked memories and the increase of area overhead is small. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TCAD.2013.2296538 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
yield enhancement,post-share redundancy scheme,integrated circuit testing,3D-stacked memories,integrated circuit reliability,Built-in self-repair (BISR),TSVs,2D memory technology,fuse architecture,three-dimensional integrated circuits,prebond repairs,faulty redundancy information,postbond repairs,mass production,through-silicon-vias,storage management chips,yield improvement,redundancy,fuse,short test algorithm,area overhead,redundancy information,redundancy analysis (RA),built-in self-test (BIST) | Journal | 33 |
Issue | ISSN | Citations |
5 | 0278-0070 | 5 |
PageRank | References | Authors |
0.46 | 15 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Changwook Lee | 1 | 20 | 7.88 |
| Wooheon Kang | 2 | 22 | 3.46 |
| Donkoo Cho | 3 | 5 | 0.46 |
| Sungho Kang | 4 | 436 | 78.44 |