| Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs | 0 | 0.34 | 2021 |
| Fail Memory Configuration Set for RA Estimation | 1 | 0.36 | 2020 |
| Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks. | 1 | 0.36 | 2020 |
| Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks | 0 | 0.34 | 2020 |
| A New Logic Topology-Based Scan Chain Stitching For Test-Power Reduction | 1 | 0.36 | 2020 |
| TSV Repair Architecture for Clustered Faults. | 1 | 0.37 | 2019 |
| Test-Friendly Data-Selectable Self-Gating (DSSG) | 0 | 0.34 | 2019 |
| Dynamic Built-In Redundancy Analysis for Memory Repair. | 1 | 0.35 | 2019 |
| Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis. | 1 | 0.36 | 2018 |
| Thermal Aware Test Scheduling for NTV Circuit. | 2 | 0.49 | 2018 |
| An Area-Efficient BIRA With 1-D Spare Segments. | 0 | 0.34 | 2018 |
| R2-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies. | 0 | 0.34 | 2017 |
| Reconfigurable Scan Architecture For Test Power And Data Volume Reduction | 0 | 0.34 | 2017 |
| Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares. | 7 | 0.56 | 2017 |
| Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation. | 0 | 0.34 | 2017 |
| A Novel X-Filling Method For Capture Power Reduction | 0 | 0.34 | 2017 |
| Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs. | 1 | 0.37 | 2017 |
| A Survey of Repair Analysis Algorithms for Memories. | 1 | 0.35 | 2016 |
| A New 3-D Fuse Architecture to Improve Yield of 3-D Memories. | 0 | 0.34 | 2016 |
| Discussion of cost-effective redundancy architectures | 0 | 0.34 | 2016 |
| P-Backtracking: A New Scan Chain Diagnosis Method With Probability | 0 | 0.34 | 2016 |
| A Test Methodology To Screen Scan-Path Failures | 0 | 0.34 | 2016 |
| Process Variation-Aware Bridge Fault Analysis | 0 | 0.34 | 2016 |
| Optimized Built-In Self-Repair for Multiple Memories. | 1 | 0.35 | 2016 |
| A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs | 1 | 0.37 | 2016 |
| Reduced-Code Test Method Using Sub-Histograms For Pipelined Adcs | 0 | 0.34 | 2015 |
| Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability | 4 | 0.41 | 2015 |
| Eco Assist Techniques through Real-time Monitoring of BEV Energy Usage Efficiency | 0 | 0.34 | 2015 |
| A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability | 3 | 0.41 | 2015 |
| Near optimal repair rate built-in redundancy analysis with very small hardware overhead | 0 | 0.34 | 2015 |
| A scan shifting method based on clock gating of multiple groups for low power scan testing | 6 | 0.47 | 2015 |
| A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories | 5 | 0.46 | 2014 |
| Recovery-Enhancing Task Scheduling For Multicore Processors Under Nbti Impact | 0 | 0.34 | 2014 |
| A Novel Test Access Mechanism For Parallel Testing Of Multi-Core System | 1 | 0.36 | 2014 |
| A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories | 4 | 0.59 | 2014 |
| Dynamic Thermal Management For 3d Multicore Processors Under Process Variations | 0 | 0.34 | 2013 |
| Thermal-Aware Dynamic Voltage Frequency Scaling For Many-Core Processors Under Process Variations | 3 | 0.42 | 2013 |
| Acceleration Of Deep Packet Inspection Using A Multi-Byte Processing Prefilter | 0 | 0.34 | 2013 |
| Built-In Self-Test For Static Adc Testing With A Triangle-Wave | 0 | 0.34 | 2013 |
| A Method For The Fast Diagnosis Of Multiple Defects Using An Efficient Candidate Selection Algorithm | 0 | 0.34 | 2012 |
| An Accurate Diagnosis Of Transition Fault Clusters Based On Single Fault Simulation | 0 | 0.34 | 2012 |
| Integration of dual channel timing formatter system for high speed memory test equipment | 11 | 1.57 | 2012 |
| An efficient IP address lookup algorithm based on a small balanced tree using entry reduction | 3 | 0.42 | 2012 |
| Noise-Tolerant Dac Bist Scheme Using Integral Calculus Approach | 0 | 0.34 | 2011 |
| Communication-aware task scheduling and voltage selection for total energy minimization in a multiprocessor system using Ant Colony Optimization. | 12 | 0.57 | 2011 |
| Path search engine for fast optimal path search using efficient hardware architecture | 0 | 0.34 | 2011 |
| EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate | 4 | 0.39 | 2010 |
| A Memory-Efficient Pattern Matching With Hardware-Based Bit-Split String Matchers For Deep Packet Inspection | 1 | 0.40 | 2010 |
| A High Performance Network-On-Chip Scheme Using Lossless Data Compression | 2 | 0.48 | 2010 |
| A Selective Scan Chain Activation Technique For Minimizing Average And Peak Power Consumption | 0 | 0.34 | 2010 |
