Name
Title | ||
|---|---|---|
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture |
Abstract | ||
|---|---|---|
This paper describes the design and implementation of the massively parallel processor based on the matrix architecture which is suitable for portable multimedia applications. The proposed architecture in this paper achieves the high performance of 40 GOPS in the case of consecutive fixed-point 16-bit additions at 200MHz clock frequency and the small power dissipation of 250mW. In addition, 1Mbit ... |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/JSSC.2006.886545 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Energy efficiency,Application software,Streaming media,Silicon,Clocks,Frequency,Power dissipation,CMOS technology,Image processing,Digital signal processing | Massively parallel,Computer science,16-bit,SIMD,CMOS,Electronic engineering,Integrated circuit,Clock rate,Memory architecture,Low-power electronics | Journal |
Volume | Issue | ISSN |
42 | 1 | 0018-9200 |
Citations | PageRank | References |
14 | 1.67 | 2 |
Authors | ||
15 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| H. Noda | 1 | 104 | 25.62 |
| Masami Nakajima | 2 | 61 | 12.45 |
| Katsumi Dosaka | 3 | 77 | 15.22 |
| Kiyoshi Nakata | 4 | 36 | 7.74 |
| Motoki Higashida | 5 | 69 | 18.31 |
| Osamu Yamamoto | 6 | 41 | 8.77 |
| Katsuya Mizumoto | 7 | 37 | 8.56 |
| Tetsushi Tanizaki | 8 | 22 | 2.56 |
| Takayuki Gyohten | 9 | 20 | 3.94 |
| Yoshihiro Okuno | 10 | 32 | 4.51 |
| Hiroyuki Kondo | 11 | 54 | 17.48 |
| Yukihiko Shimazu | 12 | 70 | 13.74 |
| Kazutami Arimoto | 13 | 95 | 29.82 |
| Kazunori Saito | 14 | 20 | 3.12 |
| Toru Shimizu | 15 | 41 | 9.45 |