Paper Info
Title
0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power
Abstract
This paper describes a radio architecture and circuit implementation results for Korea/Japan standards of 5.8 GHz DSRC systems. By characterizing specific system features concerning practical environments such as communication cell area and in-vehicle temperature, we extract detailed design specifications and show a practical system implementation. Also, we introduce a new receiver sensitivity control method which has superior signal quality over the conventional ones by gating the detected RX data with respect to the received RSSI, without degradation of receiver SNR. When the complete transceiver circuit is integrated on a chip using 0.18 mum CMOS technology, the transmitter carries up to +10.5 dBm of output power and the receiver has less than 17 dB of system noise figure. The active current consumptions are 102 mA and 52 mA during TX- and RX- modes, respectively, for 1.8V supply voltage.
Year
DOI
Venue
2008
10.1109/ISCAS.2008.4541828
ISCAS
Keywords
Field
DocType
cmos integrated circuits,transceivers,dsrc system,radio transmitters,current 102 ma,receiver sensitivity control,transmitter,transceiver circuit,frequency 5.8 ghz,voltage 1.8 v,dedicated short-range communication,size 0.18 mum,signal quality,radio architecture,radio receivers,circuit implementation,current 52 ma,cmos integrated chipset,noise figure,data mining,chip,signal to noise ratio,cmos technology,power generation,circuits,degradation
Transmitter,Transceiver,Computer science,Signal-to-noise ratio,Noise figure,Chip,CMOS,Electronic engineering,Electronic circuit,Chipset,Electrical engineering
Conference
ISSN
ISBN
Citations 
0271-4302
978-1-4244-1684-4
1
PageRank 
References 
Authors
0.39
1
7
Name
Order
Citations
PageRank
Sang-Ho Shin142041.46
Seokoh Yun282.54
Sang-Hyun Cho314321.38
Jongmoon Kim4314.64
Minseok Kang5165.56
Oh Wonkap610.39
Sung-Mo Steve Kang71198213.14