Name
Abstract | ||
|---|---|---|
We propose a novel approach to reduce overall shift power during test by inserting a predetermined amount of hardware at the output of either scan cells or internal gates. To make the proposed approach scalable, a linear time algorithm, based on an estimated dynamic power computation technique, is used to identify the nodes for hardware insertion. To avoid degrading the timing of the circuit, additional logic is added only at paths that are not timing-critical. The proposed approach significantly outperforms all approaches that gate only scan cells. Experimental results on ISCAS and ITC benchmarks show that on average more than 57% of the dynamic power can be reduced with negligible hardware overhead. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1166/jolpe.2010.1085 | JOURNAL OF LOW POWER ELECTRONICS |
Keywords | Field | DocType |
Low Power Test, Scan Shift Power Reduction, Gating Internal Nodes | Design for testing,Gating,Electronic engineering,Dynamic demand,Engineering,Time complexity,Computation,Low-power electronics,Scalability | Journal |
Volume | Issue | ISSN |
6 | 2 | 1546-1998 |
Citations | PageRank | References |
1 | 0.38 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dheepakkumaran Jayaraman | 1 | 7 | 1.54 |
| Rajamani Sethuram | 2 | 11 | 2.26 |
| Spyros Tragoudas | 3 | 625 | 88.87 |