| High-Speed Memristive Ternary Content Addressable Memory | 0 | 0.34 | 2022 |
| Resiliency of SNN on Black-Box Adversarial Attacks. | 0 | 0.34 | 2021 |
| Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays | 0 | 0.34 | 2020 |
| On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations | 0 | 0.34 | 2019 |
| Low Power Artificial Neural Network Architecture. | 0 | 0.34 | 2019 |
| A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions. | 2 | 0.39 | 2018 |
| Efficient Computation Of The Sensitization Probability Of A Critical Path Considering Process Variations And Path Correlation | 0 | 0.34 | 2017 |
| Reducing Power, Area, And Delay Of Threshold Logic Gates Considering Non-Integer Weights | 0 | 0.34 | 2017 |
| Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements. | 1 | 0.38 | 2017 |
| Efficient Critical Path Selection Under a Probabilistic Delay Model. | 2 | 0.40 | 2017 |
| More Efficient Testing of Metal-Oxide Memristor–Based Memory | 3 | 0.40 | 2017 |
| Delay Analysis for Current Mode Threshold Logic Gate Designs. | 2 | 0.42 | 2017 |
| A new method to identify threshold logic functions. | 1 | 0.37 | 2017 |
| Non-enumerative Generation of Path Delay Distributions and Its Application to Critical Path Selection. | 0 | 0.34 | 2016 |
| A Highly Robust Double Node Upset Tolerant latch | 1 | 0.37 | 2016 |
| Compressive image sensor technique with sparse measurement matrix | 0 | 0.34 | 2016 |
| Non-enumerative correlation-aware path selection | 1 | 0.35 | 2015 |
| A BIST approach for counterfeit circuit detection based on NBTI degradation | 1 | 0.37 | 2015 |
| Diagnosis of segment delay defects with current sensing | 2 | 0.39 | 2014 |
| A novel parallel adaptation of an implicit path delay grading method | 1 | 0.36 | 2014 |
| Error Correction Encoding for Tightly Coupled On-Chip Buses | 0 | 0.34 | 2014 |
| Nanopipelined threshold network synthesis | 0 | 0.34 | 2014 |
| Diagnosis of small delay defects arising due to manufacturing imperfections using path delay measurements. | 3 | 0.44 | 2013 |
| A method to determine the sensitization probability of a non-robustly testable path | 1 | 0.38 | 2013 |
| Enhanced Secure Architecture for Joint Action Test Group Systems | 14 | 1.04 | 2013 |
| Low power and high speed current-mode memristor-based TLGs. | 3 | 0.44 | 2013 |
| Error detection encoding for multi-threshold capture mechanism | 0 | 0.34 | 2013 |
| Accurate calculation of SET propagation probability for hardening | 4 | 0.60 | 2012 |
| An Online Failure Detection Method for Data Buses Using Multithreshold Receiving Logic | 0 | 0.34 | 2012 |
| Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission | 1 | 0.36 | 2012 |
| A scalable threshold logic synthesis method using ZBDDs | 4 | 0.54 | 2012 |
| A Probabilistic Approach to Diagnose SETs | 1 | 0.35 | 2011 |
| Techniques to Prioritize Paths for Diagnosis | 0 | 0.34 | 2010 |
| A data capturing method for buses on chip | 3 | 0.40 | 2010 |
| Scalable codeword generation for coupled buses | 2 | 0.40 | 2010 |
| On-line detection of random voltage perturbations in buses with multiple-threshold receivers | 1 | 0.35 | 2010 |
| Scan Shift Power Reduction By Gating Internal Nodes | 1 | 0.38 | 2010 |
| Probabilistic methods for the impact of an SET in combinational logic | 4 | 0.45 | 2010 |
| 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, 7-9 October 2009, Chicago, Illinois, USA | 56 | 6.08 | 2009 |
| Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions | 0 | 0.34 | 2009 |
| On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation | 3 | 0.41 | 2008 |
| A High-Performance Bus Architecture for Strongly Coupled Interconnects | 1 | 0.34 | 2008 |
| Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures | 0 | 0.34 | 2008 |
| A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks | 8 | 0.64 | 2008 |
| Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model | 1 | 0.36 | 2008 |
| Prioritization of Paths for Diagnosis | 2 | 0.39 | 2008 |
| A Novel Test Generation Methodology for Adaptive Diagnosis | 3 | 0.42 | 2008 |
| Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture | 2 | 0.39 | 2007 |
| Accelerating Diagnosis via Dominance Relations between Sets of Faults | 16 | 0.68 | 2007 |
| Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture | 4 | 0.44 | 2007 |
