Title
Hardware Acceleration Of Svm-Based Traffic Classification On Fpga
Abstract
Understanding the composition of the Internet traffic has many applications nowadays, mainly tracking bandwidth consuming applications, QoS-based traffic engineering and lawful interception of illegal traffic. Although many classification methods such as Support Vector Machines (SVM) have demonstrated their accuracy, not enough attention has been paid to the practical implementation of lightweight classifiers. In this paper, we consider the design of a real-time SVM classifier at many Gbps to allow online detection of categories of applications. Our solution is based on the design of a hardware accelerated SVM classifier on a FPGA board.
Year
DOI
Venue
2012
10.1109/IWCMC.2012.6314245
2012 8TH INTERNATIONAL WIRELESS COMMUNICATIONS AND MOBILE COMPUTING CONFERENCE (IWCMC)
Keywords
Field
DocType
Traffic classification, SVM, FPGA, acceleration
Traffic classification,Lawful interception,Computer science,Support vector machine,Quality of service,Field-programmable gate array,Real-time computing,Hardware acceleration,Traffic engineering,The Internet
Conference
ISSN
Citations 
PageRank 
2376-6492
10
0.57
References 
Authors
24
3
Name
Order
Citations
PageRank
Tristan Groleat1132.71
Matthieu Arzel26915.10
Sandrine Vaton321529.78