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MATTHIEU ARZEL
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Name
Affiliation
Papers
MATTHIEU ARZEL
TELECOM Bretagne, Dept Elect, F-29238 Brest 3, Brittany, France
36
Collaborators
Citations
PageRank
60
69
15.10
Referers
Referees
References
205
601
215
Search Limit
100
601
Publications (36 rows)
Collaborators (60 rows)
Referers (100 rows)
Referees (100 rows)
Title
Citations
PageRank
Year
Rethinking Weight Decay for Efficient Neural Net work Pruning
1
0.41
2022
Shuffled Decoding of Serial Concatenated Convolutional Codes
0
0.34
2021
Efficient Hardware Implementation of Incremental Learning and Inference on Chip
1
0.36
2019
40 Gop/s/mm2 fixed-point operators for Brain Computer Interface in 65 nm CMOS.
0
0.34
2018
A fully flexible circuit implementation of clique-based neural networks in 65-nm CMOS.
0
0.34
2018
Quantized Guided Pruning for Efficient Hardware Implementations of Convolutional Neural Networks.
0
0.34
2018
Transfer Incremental Learning using Data Augmentation.
0
0.34
2018
A Sub-Nj Cmos Ecg Classifier For Wireless Smart Sensor
0
0.34
2017
A 65-Nm Cmos 7fj Per Synaptic Event Clique-Based Neural Network In Scalable Architecture
0
0.34
2017
Open-source flexible packet parser for high data rate agile network probe.
0
0.34
2017
Combining FPGAs and processors for high-throughput forensics IEEE CNS 17 poster.
0
0.34
2017
An ultra-low power iterative clique-based neural network integrated in 65-nm CMOS
0
0.34
2017
A scaling-less Newton-Raphson pipelined implementation for a fixed-point inverse square root operator
1
0.37
2017
A Scaling-Less Newton-Raphson Pipelined Implementation for a Fixed-Point Reciprocal Operator.
1
0.36
2017
Incremental learning on chip.
0
0.34
2017
Budget Restricted Incremental Learning with Pre-Trained Convolutional Neural Networks and Binary Associative Memories
1
0.36
2017
AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs
1
0.37
2016
Ultra-Low-Energy Mixed-Signal IC Implementing Encoded Neural Networks.
4
0.68
2016
Low-Complexity Soft Detection of QAM Demapper for a MIMO System.
1
0.36
2016
Ouessant: Flexible Integration Of Dedicated Coprocessors In Systems On Chip
1
0.36
2016
Toward sub-pJ per classification in Body Area Sensor Networks
1
0.40
2016
Design Of Analog Subthreshold Encoded Neural Network Circuit In Sub-100nm Cmos
1
0.38
2015
Symbol-based BP detection for MIMO systems associated with non-binary LDPC codes
3
0.44
2014
Low-complexity layered BP-based detection and decoding for a NB-LDPC coded MIMO system
1
0.37
2014
Soft Error Detection and Correction Technique for Radiation Hardening Based on C-element and BICS.
5
0.53
2014
High-Speed Flow-Based Classification On Fpga
0
0.34
2014
Study of a cosmic ray impact on combinatorial logic circuits of an 8bit SAR ADC in 65nm CMOS technology
1
0.43
2013
Analog implementation of encoded neural networks.
3
0.45
2013
Analog encoded neural network for power management in MPSoC
2
0.38
2013
Flexible, extensible, open-source and affordable FPGA-based traffic generator
1
0.38
2013
Hardware Acceleration Of Svm-Based Traffic Classification On Fpga
10
0.57
2012
Adapted scheduling of QC-LDPC decoding for multistandard receivers
0
0.34
2012
A self-powered telemetry system to estimate the postoperative instability of a knee implant.
2
0.69
2011
Stochastic Decoding of Turbo Codes
21
1.17
2010
Analog decoder performance degradation due to BJTs' parasitic elements
1
0.35
2009
Semi-Iterative Analog Turbo Decoding
5
0.52
2006
1