Name
Abstract | ||
|---|---|---|
Current processors require a large number of in-flight instructions in order to look for further parallelism and hide the increasing gap between memory latency and processor cycle time. These in-flight instructions are typically stored in centralized structures called reorder buffer (ROB), which is a centerpiece to handle precise exceptions and recover a safe state in the event of a branch misprediction. However, this structure is becoming so big that it is difficult to fit it in the power budget of future processors designs. In this paper we propose a novel ROB microarchitecture named CROB (Compressed ROB) that can compress ROB entries and therefore give the illusion of having a larger virtual ROB than the number of ROB entries. The performance study of CROB shows a tremendous benefit, with an average speedup of 20% and 12% for a 128-entry and 256-entry ROB respectively. For some benchmark categories such as SpecFP2000, speedup raise up to 30%. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1145/1327171.1327176 | MEDEA '07 Proceedings of the 2007 workshop on MEmory performance: DEaling with Applications, systems and architecture |
Keywords | DocType | Citations |
larger virtual rob,instruction window,in-flight instruction,rob,average speedup,benchmark category,rob compression,large number,large instruction window,rob entry,novel rob microarchitecture,future processors design,compression,compressed rob,256-entry rob,memory latency,cycle time | Conference | 0 |
PageRank | References | Authors |
0.34 | 18 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fernando Latorre | 1 | 36 | 4.78 |
| Grigorios Magklis | 2 | 702 | 45.64 |
| José González | 3 | 526 | 35.85 |
| Pedro Chaparro | 4 | 248 | 17.27 |
| Antonio González | 5 | 3178 | 229.66 |