Paper Info
Title
Understanding the trade-offs in multi-level cell ReRAM memory design
Abstract
Resistive Random Access Memory (ReRAM) is one of the most promising emerging memory technologies as a potential replacement for DRAM memory and/or NAND Flash. Multi-level cell (MLC) ReRAM, which can store multiple bits in a single ReRAM cell, can further improve density and reduce cost-per-bit, and therefore has recently been investigated extensively. However, the majority of the prior studies on MLC ReRAM are at the device level. The design implications for MLC ReRAM at the circuit and system levels remain to be explored. This paper aim to provide the first comprehensive investigation of the design trade-offs involved in MLC ReRAM. Our study indicates that different resistance allocation schemes, programming strategies, peripheral designs, and material selections profoundly affect the area, latency, power, and reliability of MLC ReRAM. Based on this analysis, we conduct two case studies: first we compare MLC ReRAM design against MLC phase-change memory (PCM) and multi-layer cross-point ReRAM design, and point out why multi-level ReRAM is appealing; second we further explore the design space for MLC ReRAM.
Year
DOI
Venue
2013
10.1145/2463209.2488867
DAC
Keywords
Field
DocType
mlc phase-change memory,design space,multi-level cell reram memory,multi-level reram,design implication,design trade-offs,mlc reram design,multi-layer cross-point reram design,single reram cell,mlc reram,peripheral design,spintronics,memory,logic design,integrated circuit design,magnets,spin transfer torque
Logic synthesis,Design space,Multi-level cell,Computer science,Dram memory,Electronic engineering,NAND gate,Trade offs,Integrated circuit design,Resistive random-access memory
Conference
ISSN
Citations 
PageRank 
0738-100X
46
1.41
References 
Authors
6
5
Name
Order
Citations
PageRank
Cong Xu1115448.25
Dimin Niu260931.36
Naveen Muralimanohar3129557.58
Norman P. Jouppi46042791.53
Yuan Xie56430407.00