| Memristor-based affective associative memory neural network circuit with emotional gradual processes | 0 | 0.34 | 2022 |
| Memory Scaling of Cloud-Based Big Data Systems: A Hybrid Approach | 0 | 0.34 | 2022 |
| Data-Aware Storage Tiering for Deep Learning | 1 | 0.35 | 2021 |
| Survival of the Fittest Amidst the Cambrian Explosion of Processor Architectures for Artificial Intelligence : Invited Paper | 0 | 0.34 | 2021 |
| Mixed Precision Quantization for ReRAM-based DNN Inference Accelerators | 2 | 0.37 | 2021 |
| A Python-based High-Level Programming Flow for CPU-FPGA Heterogeneous Systems : (Invited Paper) | 0 | 0.34 | 2021 |
| Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory. | 0 | 0.34 | 2019 |
| Toward Cost-Effective Memory Scaling in Clouds: Symbiosis of Virtual and Physical Memory | 0 | 0.34 | 2018 |
| SmoothOut: Smoothing Out Sharp Minima for Generalization in Large-Batch Deep Learning. | 0 | 0.34 | 2018 |
| TernGrad: Ternary Gradients to Reduce Communication in Distributed Deep Learning. | 52 | 1.31 | 2017 |
| Coordinating Filters for Faster Deep Neural Networks | 12 | 0.52 | 2017 |
| NVSim-VXs: an improved NVSim for variation aware STT-RAM simulation | 1 | 0.37 | 2016 |
| NVSim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory. | 5 | 0.48 | 2016 |
| BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories. | 0 | 0.34 | 2016 |
| Pinatubo: A Processing-In-Memory Architecture For Bulk Bitwise Operations In Emerging Non-Volatile Memories | 40 | 1.14 | 2016 |
| PRIME: A Novel Processing-in-Memory Architecture for Neural Network Computation in ReRAM-Based Main Memory. | 139 | 3.32 | 2016 |
| History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures | 2 | 0.37 | 2015 |
| Overcoming the challenges of crossbar resistive memory architectures | 83 | 2.68 | 2015 |
| Memory and Storage System Design with Nonvolatile Memory Technologies. | 4 | 0.48 | 2015 |
| Impact of Cell Failure on Reliable Cross-Point Resistive Memory Design | 7 | 0.53 | 2015 |
| Impact of Write Pulse and Process Variation on 22 nm FinFET-Based STT-RAM Design: A Device-Architecture Co-Optimization Approach. | 5 | 0.45 | 2015 |
| Modeling framework for cross-point resistive memory design emphasizing reliability and variability issues | 6 | 0.51 | 2015 |
| TSV power supply array electromigration lifetime analysis in 3D ICS | 0 | 0.34 | 2014 |
| 3D-SWIFT: a high-performance 3D-stacked wide IO DRAM | 14 | 0.65 | 2014 |
| CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture | 16 | 0.65 | 2014 |
| Modeling and design analysis of 3D vertical resistive memory — A low cost cross-point architecture | 8 | 0.58 | 2014 |
| Half-DRAM: a high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation | 33 | 1.05 | 2014 |
| Architecting 3D vertical resistive memory for next-generation storage systems | 12 | 0.64 | 2014 |
| Reliability-aware cross-point resistive memory design | 2 | 0.38 | 2014 |
| Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing | 10 | 0.55 | 2014 |
| Adaptive placement and migration policy for an STT-RAM-based hybrid cache | 46 | 1.23 | 2014 |
| Low Power Multi-Level-Cell Resistive Memory Design With Incomplete Data Mapping | 14 | 0.59 | 2013 |
| Design of cross-point metal-oxide ReRAM emphasizing reliability and cost | 14 | 1.75 | 2013 |
| Understanding the trade-offs in multi-level cell ReRAM memory design | 46 | 1.41 | 2013 |
| Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM system | 1 | 0.39 | 2013 |
| Design trade-offs for high density cross-point resistive memory | 36 | 1.92 | 2012 |
| Modeling and design exploration of FBDRAM as on-chip memory | 3 | 0.39 | 2012 |
| Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs | 120 | 3.38 | 2012 |
| NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory | 327 | 10.86 | 2012 |
| Bandwidth-aware reconfigurable cache design with hybrid memory technologies | 13 | 0.54 | 2011 |
| Device-architecture co-optimization of STT-RAM based memory for low power embedded systems | 22 | 1.19 | 2011 |
| Moguls: A model to explore the memory hierarchy for bandwidth improvements | 12 | 0.77 | 2011 |
| Impact of process variations on emerging memristor | 46 | 3.40 | 2010 |
