Paper Info
Title
Fine grain incremental rescheduling via architectural retiming
Abstract
With the decreasing feature sizes during VLSI fabricationand the dominance of interconnect delay over that of gates,control logic and wiring no longer have a negligible impacton delay and area. The need thus arises for developing techniquesand tools to redesign incrementally to eliminate performancebottlenecks.Such a redesign e#ort corresponds toincrementally modifying an existing schedule obtained viahigh-level synthesis. In this paper we demonstrate that applyingarchitectural...
Year
DOI
Venue
1998
10.1109/ISSS.1998.730619
ISSS
Keywords
Field
DocType
fine grain,architectural retiming,incremental rescheduling,high level synthesis,very large scale integration,logic design,fabrication,vlsi,logic gates
Logic synthesis,Pipeline (computing),Retiming,Computer science,High-level synthesis,Correctness,Parallel computing,Real-time computing,Control logic,Cycles per instruction,Very-large-scale integration
Conference
ISSN
ISBN
Citations 
1080-1820
0-8186-8623-5
7
PageRank 
References 
Authors
0.65
8
1
Name
Order
Citations
PageRank
Soha Hassoun1535241.27