Name
Abstract | ||
|---|---|---|
This paper presents a SystemC-based approach for system-level design of partially reconfigurable hardware. The main focuses are resource estimation to support system analysis, reconfiguration modeling for fast performance simulation, automatic generation of reconfigurable components and a static prefetch scheduler. The approach was applied in a real design case of a part of a WCDMA decoding algorithm on a commercial reconfigurable platform. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/ISCAS.2007.378619 | ISCAS |
Keywords | Field | DocType |
reconfiguration modeling,static prefetch scheduler,wcdma decoding algorithm,system-level design,specification languages,systemc-,code division multiple access,reconfigurable component automatic generation,electronic design automation,resource estimation,high level synthesis,partially reconfigurable hardware,decoding,system analysis,circuit simulation,field programmable gate arrays,space technology,silicon,system level design,application specific integrated circuits,design methodology,hardware | Computer architecture,Computer science,High-level synthesis,Electronic system-level design and verification,Field-programmable gate array,SystemC,Electronic design automation,Instruction prefetch,Control reconfiguration,Reconfigurable computing,Embedded system | Conference |
ISSN | ISBN | Citations |
0271-4302 | 1-4244-0921-7 | 0 |
PageRank | References | Authors |
0.34 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yang Qu | 1 | 103 | 10.67 |
| Kari Tiensyrjä | 2 | 42 | 10.53 |
| Juha-Pekka Soininen | 3 | 147 | 23.41 |
| Jari Nurmi | 4 | 556 | 83.87 |