Name
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/SOCC.2012.6398382 | SoCC |
Keywords | Field | DocType |
CMOS integrated circuits,Monte Carlo methods,SRAM chips,amplifiers,low-power electronics,system-on-chip,Monte Carlo simulations,SRAM array,SRAM macro,SRAM read failure,SRAM reliability,SoC yield,bitline differential voltage,cell data level degradation,low voltage-operated SRAM,mismatch variation,nanometer CMOS technology,read-assist write-back voltage sense amplifier,timing-insensitive SA scheme,typical 6T-SRAM column,voltage 500 mV | Sense amplifier,Computer science,Voltage,Real-time computing,CMOS,Electronic engineering,Static random-access memory,Low voltage,Sense (electronics),Amplifier,Low-power electronics | Conference |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tahseen Shakir | 1 | 4 | 0.79 |
| Manoj Sachdev | 2 | 669 | 88.45 |