Name
Title | ||
|---|---|---|
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs |
Abstract | ||
|---|---|---|
A Taylor Expansion Diagram (TED) is a compact, word-level, canonical representation for data flow computations that can be expressed as multivariate polynomials. TEDs are based on a decomposition scheme using Taylor series expansion that allows one to model word-level signals as algebraic symbols. This power of abstraction, combined with the canonicity and compactness of TED, makes it applicable to equivalence verification of dataflow designs. The paper describes the theory of TEDs and proves their canonicity. It shows how to construct a TED from an HDL design specification and discusses the application of TEDs in proving the equivalence of such designs. Experiments were performed with a variety of designs to observe the potential and limitations of TEDs for dataflow design verification. Application of TEDs to algorithmic and behavioral verification is demonstrated. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TC.2006.153 | IEEE Trans. Computers |
Keywords | Field | DocType |
word-level signal,taylor series expansion,dataflow design verification,canonical representation,taylor expansion,algebraic symbol,data flow computation,behavioral verification,dataflow design,hdl design specification,taylor expansion diagrams,data flow designs,data flow,verification,formal verification,register transfer level,equivalence classes,hardware description languages | Algebra,Computer science,Parallel computing,Algorithm,Canonical form,Equivalence (measure theory),Dataflow,Equivalence class,Taylor series,Formal verification,Data flow diagram,Hardware description language | Journal |
Volume | Issue | ISSN |
55 | 9 | 0018-9340 |
Citations | PageRank | References |
31 | 1.36 | 41 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Maciej J. Ciesielski | 1 | 629 | 74.80 |
| Priyank Kalla | 2 | 275 | 27.07 |
| Serkan Askar | 3 | 50 | 3.01 |