Name
Abstract | ||
|---|---|---|
Using a cache vulnerability factor to measure the susceptibility of cache memories to transient errors at the architecture level can help designers make appropriate cost and reliability trade-offs at early design cycles. Two early write-back strategies can also improve the reliability of write-back data caches without compromising performance. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/MDT.2009.29 | IEEE Design & Test of Computers |
Keywords | Field | DocType |
cache storage,early design cycle,minimizing cache vulnerability,early write-back strategy,cache vulnerability factor,write-back data cache,transient errors,reliability,cache memories,appropriate cost,reliability trade-offs,cache memory,transient error,cache vulnerability,architecture level | Cache invalidation,Cache pollution,Cache,Computer science,Cache-only memory architecture,Real-time computing,Cache algorithms,Cache coloring,Bus sniffing,Smart Cache,Computer engineering,Reliability engineering | Journal |
Volume | Issue | ISSN |
26 | 2 | 0740-7475 |
Citations | PageRank | References |
3 | 0.41 | 0 |
Authors | ||
1 | ||