Name
Affiliation
Papers
WEI ZHANG
So Illinois Univ, Dept Elect & Comp Engn, Carbondale, IL 62902 USA
21
Collaborators
Citations 
PageRank 
10
163
11.75
Referers 
Referees 
References 
382
526
277
Search Limit
100526
Title
Citations
PageRank
Year
A time-predictable dual-core prototype on FPGA00.342010
Review of Parallel Techniques and its Implication for Java00.342010
Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time20.392010
Time-Predictable L2 Cache Design for High-Performance Real-Time Systems30.382010
Exploiting Multi-core Processors to Improve Time Predictability for Real-Time Java Computing10.342009
Studying Energy-Oriented Dynamic Optimizations in Java Virtual Machines00.342009
Boosting the Performance of Software-Based Transient Errors Tolerant Techniques through Compiler Optimizations00.342009
Static worst-case energy and lifetime estimation of wireless sensor networks110.772009
Improving Java performance and energy dissipation through efficient code caching10.352009
Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches200.952009
Computing and Minimizing Cache Vulnerability to Transient Errors30.412009
Adaptive Drowsy Cache Control for Java Applications00.342008
A time-predictable VLIW processor and its compiler support70.502008
Exploiting virtual registers to reduce pressure on real registers70.442008
Analyzing the worst-case execution time for instruction caches with prefetching10.352008
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches792.892008
Compiler-Assisted Leakage Energy Reduction for Cache Memories00.342007
Exploiting the replication cache to improve cache read bandwidth cost effectively00.342006
Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed Resizing00.342006
Computing Cache Vulnerability to Transient Errors and Its Implication260.892005
Replica Victim Caching to Improve Reliability of In-Cache Replication20.402004